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Commit c063d1f8 authored by Dhaval Patel's avatar Dhaval Patel
Browse files

drm/msm: update rsc timers back to recommended settings 



Update rsc timers to hardware programming recommendation
value - 1ms for each TCS transfer. This change also
update the rsc_mode threshold value greater than TCS transfer
value. With this patch, mode-0 may not be selected
between pingpong done and next vsync and that may lead to
frame drop.

Change-Id: Id72c92760e3a90b762a7c2a19da51dda8bf31973
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 5430b543

drivers/gpu/drm/msm/sde_rsc.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -30,14 +30,14 @@ 
#include "sde_rsc_priv.h"

#include "sde_rsc_priv.h"

#include "sde_dbg.h"

#include "sde_dbg.h"





/* worst case time to execute the one tcs vote(sleep/wake) - ~0.2ms */

/* worst case time to execute the one tcs vote(sleep/wake) - ~1ms */

#define SINGLE_TCS_EXECUTION_TIME				200000

#define SINGLE_TCS_EXECUTION_TIME				1064000





/* this time is ~1ms - only wake tcs in any mode */

/* this time is ~1ms - only wake tcs in any mode */

#define RSC_BACKOFF_TIME_NS		 (SINGLE_TCS_EXECUTION_TIME + 100)

#define RSC_BACKOFF_TIME_NS		 (SINGLE_TCS_EXECUTION_TIME + 100)





/* this time is ~1ms - only wake TCS in mode-0 */

/* this time is ~1ms - only wake TCS in mode-0 */

#define RSC_MODE_THRESHOLD_TIME_IN_NS	((SINGLE_TCS_EXECUTION_TIME >> 1) + 100)

#define RSC_MODE_THRESHOLD_TIME_IN_NS	(SINGLE_TCS_EXECUTION_TIME + 100)





/* this time is ~2ms - sleep+ wake TCS in mode-1 */

/* this time is ~2ms - sleep+ wake TCS in mode-1 */

#define RSC_TIME_SLOT_0_NS		((SINGLE_TCS_EXECUTION_TIME * 2) + 100)

#define RSC_TIME_SLOT_0_NS		((SINGLE_TCS_EXECUTION_TIME * 2) + 100)

drivers/gpu/drm/msm/sde_rsc_hw.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -206,7 +206,7 @@ static int rsc_hw_seq_memory_init(struct sde_rsc_priv *rsc) 
	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x30,

						0xa7e9a920, rsc->debug_mode);

						0xa7e9a920, rsc->debug_mode);

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x34,

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_MEM_0_DRV0 + 0x34,

						0x002079e7, rsc->debug_mode);

						0x002089e7, rsc->debug_mode);





	/* branch address */

	/* branch address */

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,

	dss_reg_w(&rsc->drv_io, SDE_RSCC_SEQ_CFG_BR_ADDR_0_DRV0,