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Commit c032524f authored by Paul Mackerras's avatar Paul Mackerras
Browse files

powerpc: Make single-stepping emulation (mostly) usable on 32-bit 



The sc instruction emulation can't be done the same way on 32-bit
as 64-bit yet, but this should work OK.

Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent d73e0c99

arch/powerpc/lib/sstep.c

+17 −0
Original line number Diff line number Diff line
@@ -10,13 +10,18 @@ 
 */

#include <linux/kernel.h>

#include <linux/ptrace.h>

#include <linux/config.h>

#include <asm/sstep.h>

#include <asm/processor.h>



extern char system_call_common[];



#ifdef CONFIG_PPC64

/* Bits in SRR1 that are copied from MSR */

#define MSR_MASK	0xffffffff87c0ffff

#else

#define MSR_MASK	0x87c0ffff

#endif



/*

 * Determine whether a conditional branch instruction would branch.
@@ -66,6 +71,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) 
		if (branch_taken(instr, regs))

			regs->nip = imm;

		return 1;

#ifdef CONFIG_PPC64

	case 17:	/* sc */

		/*

		 * N.B. this uses knowledge about how the syscall
@@ -79,6 +85,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) 
		regs->nip = (unsigned long) &system_call_common;

		regs->msr = MSR_KERNEL;

		return 1;

#endif

	case 18:	/* b */

		imm = instr & 0x03fffffc;

		if (imm & 0x02000000)
@@ -121,6 +128,15 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) 
			if ((regs->msr & MSR_SF) == 0)

				regs->nip &= 0xffffffffUL;

			return 1;

		case 0x124:	/* mtmsr */

			imm = regs->gpr[rd];

			if ((imm & MSR_RI) == 0)

				/* can't step mtmsr that would clear MSR_RI */

				return -1;

			regs->msr = imm;

			regs->nip += 4;

			return 1;

#ifdef CONFIG_PPC64

		case 0x164:	/* mtmsrd */

			/* only MSR_EE and MSR_RI get changed if bit 15 set */

			/* mtmsrd doesn't change MSR_HV and MSR_ME */
@@ -135,6 +151,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) 
			if ((imm & MSR_SF) == 0)

				regs->nip &= 0xffffffffUL;

			return 1;

#endif

		}

	}

	return 0;

include/asm-powerpc/reg.h

+8 −0
Original line number Diff line number Diff line
@@ -51,9 +51,17 @@ 
#define __MASK(X)	(1UL<<(X))

#endif



#ifdef CONFIG_PPC64

#define MSR_SF		__MASK(MSR_SF_LG)	/* Enable 64 bit mode */

#define MSR_ISF		__MASK(MSR_ISF_LG)	/* Interrupt 64b mode valid on 630 */

#define MSR_HV 		__MASK(MSR_HV_LG)	/* Hypervisor state */

#else

/* so tests for these bits fail on 32-bit */

#define MSR_SF		0

#define MSR_ISF		0

#define MSR_HV		0

#endif



#define MSR_VEC		__MASK(MSR_VEC_LG)	/* Enable AltiVec */

#define MSR_POW		__MASK(MSR_POW_LG)	/* Enable Power Management */

#define MSR_WE		__MASK(MSR_WE_LG)	/* Wait State Enable */

include/asm-ppc64/sstep.h→include/asm-powerpc/sstep.h

+3 −1
Original line number Diff line number Diff line
@@ -16,8 +16,10 @@ struct pt_regs; 
 * we don't allow putting a breakpoint on an mtmsrd instruction.

 * Similarly we don't allow breakpoints on rfid instructions.

 * These macros tell us if an instruction is a mtmsrd or rfid.

 * Note that IS_MTMSRD returns true for both an mtmsr (32-bit)

 * and an mtmsrd (64-bit).

 */

#define IS_MTMSRD(instr)	(((instr) & 0xfc0007fe) == 0x7c000164)

#define IS_MTMSRD(instr)	(((instr) & 0xfc0007be) == 0x7c000124)

#define IS_RFID(instr)		(((instr) & 0xfc0007fe) == 0x4c000024)



/* Emulate instructions that cause a transfer of control. */