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Commit c00193f9 authored by Ingo Molnar's avatar Ingo Molnar
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Merge branches 'oprofile-v2' and 'timers/hpet' into x86/core-v4

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@@ -159,8 +159,6 @@ hayes-esp.txt
	- info on using the Hayes ESP serial driver.
highuid.txt
	- notes on the change from 16 bit to 32 bit user/group IDs.
hpet.txt
	- High Precision Event Timer Driver for Linux.
timers/
	- info on the timer related topics
hw_random.txt
+10 −0
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00-INDEX
	- this file
highres.txt
	- High resolution timers and dynamic ticks design notes
hpet.txt
	- High Precision Event Timer Driver for Linux
hrtimers.txt
	- subsystem for high-resolution kernel timers
timer_stats.txt
	- timer usage statistics
+21 −22
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		High Precision Event Timer Driver for Linux

The High Precision Event Timer (HPET) hardware is the future replacement
for the 8254 and Real Time Clock (RTC) periodic timer functionality.
Each HPET can have up to 32 timers.  It is possible to configure the
first two timers as legacy replacements for 8254 and RTC periodic timers.
A specification done by Intel and Microsoft can be found at
<http://www.intel.com/technology/architecture/hpetspec.htm>.
The High Precision Event Timer (HPET) hardware follows a specification
by Intel and Microsoft which can be found at

	http://www.intel.com/technology/architecture/hpetspec.htm

Each HPET has one fixed-rate counter (at 10+ MHz, hence "High Precision")
and up to 32 comparators.  Normally three or more comparators are provided,
each of which can generate oneshot interupts and at least one of which has
additional hardware to support periodic interrupts.  The comparators are
also called "timers", which can be misleading since usually timers are
independent of each other ... these share a counter, complicating resets.

HPET devices can support two interrupt routing modes.  In one mode, the
comparators are additional interrupt sources with no particular system
role.  Many x86 BIOS writers don't route HPET interrupts at all, which
prevents use of that mode.  They support the other "legacy replacement"
mode where the first two comparators block interrupts from 8254 timers
and from the RTC.

The driver supports detection of HPET driver allocation and initialization
of the HPET before the driver module_init routine is called.  This enables
platform code which uses timer 0 or 1 as the main timer to intercept HPET
initialization.  An example of this initialization can be found in
arch/i386/kernel/time_hpet.c.
arch/x86/kernel/hpet.c.

The driver provides two APIs which are very similar to the API found in
the rtc.c driver.  There is a user space API and a kernel space API.
An example user space program is provided below.
The driver provides a userspace API which resembles the API found in the
RTC driver framework.  An example user space program is provided below.

#include <stdio.h>
#include <stdlib.h>
@@ -286,15 +297,3 @@ out:

	return;
}

The kernel API has three interfaces exported from the driver:

	hpet_register(struct hpet_task *tp, int periodic)
	hpet_unregister(struct hpet_task *tp)
	hpet_control(struct hpet_task *tp, unsigned int cmd, unsigned long arg)

The kernel module using this interface fills in the ht_func and ht_data
members of the hpet_task structure before calling hpet_register.
hpet_control simply vectors to the hpet_ioctl routine and has the same
commands and respective arguments as the user API.  hpet_unregister
is used to terminate usage of the HPET timer reserved by hpet_register.
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@@ -13,6 +13,20 @@ config OPROFILE

	  If unsure, say N.

config OPROFILE_IBS
	bool "OProfile AMD IBS support (EXPERIMENTAL)"
	default n
	depends on OPROFILE && SMP && X86
	help
          Instruction-Based Sampling (IBS) is a new profiling
          technique that provides rich, precise program performance
          information. IBS is introduced by AMD Family10h processors
          (AMD Opteron Quad-Core processor “Barcelona”) to overcome
          the limitations of conventional performance counter
          sampling.

	  If unsure, say N.

config HAVE_OPROFILE
	def_bool n

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@@ -295,6 +295,9 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
 *
 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
 * MCE interrupts are supported. Thus MCE offset must be set to 0.
 *
 * If mask=1, the LVT entry does not generate interrupts while mask=0
 * enables the vector. See also the BKDGs.
 */

#define APIC_EILVT_LVTOFF_MCE 0
@@ -319,6 +322,7 @@ u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
	setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
	return APIC_EILVT_LVTOFF_IBS;
}
EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);

/*
 * Program the next event, relative to now
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