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Commit bf856fbb authored by Boojin Kim's avatar Boojin Kim Committed by Vinod Koul
Browse files

ARM: EXYNOS4: Use generic DMA PL330 driver 



This patch makes Samsung EXYNOS4 to use DMA PL330 driver
on DMADEVICE. The EXYNOS4 uses DMA generic APIs instead of
SAMSUNG specific S3C-PL330 APIs.

Signed-off-by: default avatarBoojin Kim <boojin.kim@samsung.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Acked-by: default avatarVinod Koul <vinod.koul@intel.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent c4e16625

arch/arm/mach-exynos4/Kconfig

+1 −1
Original line number Original line Diff line number Diff line
@@ -11,7 +11,7 @@ if ARCH_EXYNOS4 




config CPU_EXYNOS4210

config CPU_EXYNOS4210

	bool

	bool

	select S3C_PL330_DMA

	select SAMSUNG_DMADEV

	help

	help

	  Enable EXYNOS4210 CPU support

	  Enable EXYNOS4210 CPU support

arch/arm/mach-exynos4/clock.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -43,6 +43,11 @@ static struct clk clk_sclk_usbphy1 = { 
	.name		= "sclk_usbphy1",

	.name		= "sclk_usbphy1",

};

};





static struct clk dummy_apb_pclk = {

	.name		= "apb_pclk",

	.id		= -1,

};



static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)

static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)

{

{

	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);

	return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
@@ -454,12 +459,12 @@ static struct clk init_clocks_off[] = { 
		.enable		= exynos4_clk_ip_fsys_ctrl,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 10),

		.ctrlbit	= (1 << 10),

	}, {

	}, {

		.name		= "pdma",

		.name		= "dma",

		.devname	= "s3c-pl330.0",

		.devname	= "s3c-pl330.0",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 0),

		.ctrlbit	= (1 << 0),

	}, {

	}, {

		.name		= "pdma",

		.name		= "dma",

		.devname	= "s3c-pl330.1",

		.devname	= "s3c-pl330.1",

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.enable		= exynos4_clk_ip_fsys_ctrl,

		.ctrlbit	= (1 << 1),

		.ctrlbit	= (1 << 1),
@@ -1210,5 +1215,7 @@ void __init exynos4_register_clocks(void) 
	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));

	s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));





	s3c24xx_register_clock(&dummy_apb_pclk);



	s3c_pwmclk_init();

	s3c_pwmclk_init();

}
 
}

arch/arm/mach-exynos4/dma.c

+188 −111
Original line number Original line Diff line number Diff line
@@ -21,151 +21,228 @@ 
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

 */

 */





#include <linux/platform_device.h>

#include <linux/dma-mapping.h>

#include <linux/dma-mapping.h>

#include <linux/amba/bus.h>

#include <linux/amba/pl330.h>





#include <asm/irq.h>

#include <plat/devs.h>

#include <plat/devs.h>

#include <plat/irqs.h>

#include <plat/irqs.h>





#include <mach/map.h>

#include <mach/map.h>

#include <mach/irqs.h>

#include <mach/irqs.h>



#include <mach/dma.h>

#include <plat/s3c-pl330-pdata.h>





static u64 dma_dmamask = DMA_BIT_MASK(32);

static u64 dma_dmamask = DMA_BIT_MASK(32);





static struct resource exynos4_pdma0_resource[] = {

struct dma_pl330_peri pdma0_peri[28] = {

	[0] = {

	{

		.start	= EXYNOS4_PA_PDMA0,

		.peri_id = (u8)DMACH_PCM0_RX,

		.end	= EXYNOS4_PA_PDMA0 + SZ_4K,

		.rqtype = DEVTOMEM,

		.flags	= IORESOURCE_MEM,

	}, {

	},

		.peri_id = (u8)DMACH_PCM0_TX,

	[1] = {

		.rqtype = MEMTODEV,

		.start	= IRQ_PDMA0,

	}, {

		.end	= IRQ_PDMA0,

		.peri_id = (u8)DMACH_PCM2_RX,

		.flags	= IORESOURCE_IRQ,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_PCM2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ0,

	}, {

		.peri_id = (u8)DMACH_MSM_REQ2,

	}, {

		.peri_id = (u8)DMACH_SPI0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SPI0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SPI2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SPI2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0S_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_I2S0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_I2S0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART4_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART4_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS2_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS2_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS4_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS4_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_AC97_MICIN,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_AC97_PCMIN,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_AC97_PCMOUT,

		.rqtype = MEMTODEV,

	},

	},

};

};





static struct s3c_pl330_platdata exynos4_pdma0_pdata = {

struct dma_pl330_platdata exynos4_pdma0_pdata = {

	.peri = {

	.nr_valid_peri = ARRAY_SIZE(pdma0_peri),

		[0] = DMACH_PCM0_RX,

	.peri = pdma0_peri,

		[1] = DMACH_PCM0_TX,

		[2] = DMACH_PCM2_RX,

		[3] = DMACH_PCM2_TX,

		[4] = DMACH_MSM_REQ0,

		[5] = DMACH_MSM_REQ2,

		[6] = DMACH_SPI0_RX,

		[7] = DMACH_SPI0_TX,

		[8] = DMACH_SPI2_RX,

		[9] = DMACH_SPI2_TX,

		[10] = DMACH_I2S0S_TX,

		[11] = DMACH_I2S0_RX,

		[12] = DMACH_I2S0_TX,

		[13] = DMACH_I2S2_RX,

		[14] = DMACH_I2S2_TX,

		[15] = DMACH_UART0_RX,

		[16] = DMACH_UART0_TX,

		[17] = DMACH_UART2_RX,

		[18] = DMACH_UART2_TX,

		[19] = DMACH_UART4_RX,

		[20] = DMACH_UART4_TX,

		[21] = DMACH_SLIMBUS0_RX,

		[22] = DMACH_SLIMBUS0_TX,

		[23] = DMACH_SLIMBUS2_RX,

		[24] = DMACH_SLIMBUS2_TX,

		[25] = DMACH_SLIMBUS4_RX,

		[26] = DMACH_SLIMBUS4_TX,

		[27] = DMACH_AC97_MICIN,

		[28] = DMACH_AC97_PCMIN,

		[29] = DMACH_AC97_PCMOUT,

		[30] = DMACH_MAX,

		[31] = DMACH_MAX,

	},

};

};





static struct platform_device exynos4_device_pdma0 = {

struct amba_device exynos4_device_pdma0 = {

	.name		= "s3c-pl330",

	.id		= 0,

	.num_resources	= ARRAY_SIZE(exynos4_pdma0_resource),

	.resource	= exynos4_pdma0_resource,

	.dev = {

	.dev = {

		.init_name = "dma-pl330.0",

		.dma_mask = &dma_dmamask,

		.dma_mask = &dma_dmamask,

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.platform_data = &exynos4_pdma0_pdata,

		.platform_data = &exynos4_pdma0_pdata,

	},

	},

};

	.res = {



		.start = EXYNOS4_PA_PDMA0,

static struct resource exynos4_pdma1_resource[] = {

		.end = EXYNOS4_PA_PDMA0 + SZ_4K,

	[0] = {

		.start	= EXYNOS4_PA_PDMA1,

		.end	= EXYNOS4_PA_PDMA1 + SZ_4K,

		.flags = IORESOURCE_MEM,

		.flags = IORESOURCE_MEM,

	},

	},

	[1] = {

	.irq = {IRQ_PDMA0, NO_IRQ},

		.start	= IRQ_PDMA1,

	.periphid = 0x00041330,

		.end	= IRQ_PDMA1,

		.flags	= IORESOURCE_IRQ,

	},

};

};





static struct s3c_pl330_platdata exynos4_pdma1_pdata = {

struct dma_pl330_peri pdma1_peri[25] = {

	.peri = {

	{

		[0] = DMACH_PCM0_RX,

		.peri_id = (u8)DMACH_PCM0_RX,

		[1] = DMACH_PCM0_TX,

		.rqtype = DEVTOMEM,

		[2] = DMACH_PCM1_RX,

	}, {

		[3] = DMACH_PCM1_TX,

		.peri_id = (u8)DMACH_PCM0_TX,

		[4] = DMACH_MSM_REQ1,

		.rqtype = MEMTODEV,

		[5] = DMACH_MSM_REQ3,

	}, {

		[6] = DMACH_SPI1_RX,

		.peri_id = (u8)DMACH_PCM1_RX,

		[7] = DMACH_SPI1_TX,

		.rqtype = DEVTOMEM,

		[8] = DMACH_I2S0S_TX,

	}, {

		[9] = DMACH_I2S0_RX,

		.peri_id = (u8)DMACH_PCM1_TX,

		[10] = DMACH_I2S0_TX,

		.rqtype = MEMTODEV,

		[11] = DMACH_I2S1_RX,

	}, {

		[12] = DMACH_I2S1_TX,

		.peri_id = (u8)DMACH_MSM_REQ1,

		[13] = DMACH_UART0_RX,

	}, {

		[14] = DMACH_UART0_TX,

		.peri_id = (u8)DMACH_MSM_REQ3,

		[15] = DMACH_UART1_RX,

	}, {

		[16] = DMACH_UART1_TX,

		.peri_id = (u8)DMACH_SPI1_RX,

		[17] = DMACH_UART3_RX,

		.rqtype = DEVTOMEM,

		[18] = DMACH_UART3_TX,

	}, {

		[19] = DMACH_SLIMBUS1_RX,

		.peri_id = (u8)DMACH_SPI1_TX,

		[20] = DMACH_SLIMBUS1_TX,

		.rqtype = MEMTODEV,

		[21] = DMACH_SLIMBUS3_RX,

	}, {

		[22] = DMACH_SLIMBUS3_TX,

		.peri_id = (u8)DMACH_I2S0S_TX,

		[23] = DMACH_SLIMBUS5_RX,

		.rqtype = MEMTODEV,

		[24] = DMACH_SLIMBUS5_TX,

	}, {

		[25] = DMACH_SLIMBUS0AUX_RX,

		.peri_id = (u8)DMACH_I2S0_RX,

		[26] = DMACH_SLIMBUS0AUX_TX,

		.rqtype = DEVTOMEM,

		[27] = DMACH_SPDIF,

	}, {

		[28] = DMACH_MAX,

		.peri_id = (u8)DMACH_I2S0_TX,

		[29] = DMACH_MAX,

		.rqtype = MEMTODEV,

		[30] = DMACH_MAX,

	}, {

		[31] = DMACH_MAX,

		.peri_id = (u8)DMACH_I2S1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_I2S1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART0_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART0_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_UART3_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_UART3_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS1_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS1_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS3_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS3_TX,

		.rqtype = MEMTODEV,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS5_RX,

		.rqtype = DEVTOMEM,

	}, {

		.peri_id = (u8)DMACH_SLIMBUS5_TX,

		.rqtype = MEMTODEV,

	},

	},

};

};





static struct platform_device exynos4_device_pdma1 = {

struct dma_pl330_platdata exynos4_pdma1_pdata = {

	.name		= "s3c-pl330",

	.nr_valid_peri = ARRAY_SIZE(pdma1_peri),

	.id		= 1,

	.peri = pdma1_peri,

	.num_resources	= ARRAY_SIZE(exynos4_pdma1_resource),

};

	.resource	= exynos4_pdma1_resource,



struct amba_device exynos4_device_pdma1 = {

	.dev = {

	.dev = {

		.init_name = "dma-pl330.1",

		.dma_mask = &dma_dmamask,

		.dma_mask = &dma_dmamask,

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.coherent_dma_mask = DMA_BIT_MASK(32),

		.platform_data = &exynos4_pdma1_pdata,

		.platform_data = &exynos4_pdma1_pdata,

	},

	},

};

	.res = {



		.start = EXYNOS4_PA_PDMA1,

static struct platform_device *exynos4_dmacs[] __initdata = {

		.end = EXYNOS4_PA_PDMA1 + SZ_4K,

	&exynos4_device_pdma0,

		.flags = IORESOURCE_MEM,

	&exynos4_device_pdma1,

	},

	.irq = {IRQ_PDMA1, NO_IRQ},

	.periphid = 0x00041330,

};

};





static int __init exynos4_dma_init(void)

static int __init exynos4_dma_init(void)

{

{

	platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));

	amba_device_register(&exynos4_device_pdma0, &iomem_resource);





	return 0;

	return 0;

}

}