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Commit bf7f1c7e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "A bogus warning fix, a counter width handling fix affecting certain
  machines, plus a oneliner hw-enablement patch for Knights Mill CPUs"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/core: Remove invalid warning from list_update_cgroup_even()t
  perf/x86: Fix full width counter, counter overflow
  perf/x86/intel: Enable C-state residency events for Knights Mill
parents 5b43f97f 8fc31ce8

arch/x86/events/core.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -69,7 +69,7 @@ u64 x86_perf_event_update(struct perf_event *event) 
	int shift = 64 - x86_pmu.cntval_bits;

	int shift = 64 - x86_pmu.cntval_bits;

	u64 prev_raw_count, new_raw_count;

	u64 prev_raw_count, new_raw_count;

	int idx = hwc->idx;

	int idx = hwc->idx;

	s64 delta;

	u64 delta;





	if (idx == INTEL_PMC_IDX_FIXED_BTS)

	if (idx == INTEL_PMC_IDX_FIXED_BTS)

		return 0;

		return 0;

arch/x86/events/intel/core.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void) 




	/* Support full width counters using alternative MSR range */

	/* Support full width counters using alternative MSR range */

	if (x86_pmu.intel_cap.full_width_write) {

	if (x86_pmu.intel_cap.full_width_write) {

		x86_pmu.max_period = x86_pmu.cntval_mask;

		x86_pmu.max_period = x86_pmu.cntval_mask >> 1;

		x86_pmu.perfctr = MSR_IA32_PMC0;

		x86_pmu.perfctr = MSR_IA32_PMC0;

		pr_cont("full-width counters, ");

		pr_cont("full-width counters, ");

	}

	}

arch/x86/events/intel/cstate.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -540,6 +540,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),





	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),

	{ },

	{ },

};

};

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);

kernel/events/core.c

+8 −11
Original line number Original line Diff line number Diff line
@@ -903,17 +903,14 @@ list_update_cgroup_event(struct perf_event *event, 
	 */

	 */

	cpuctx = __get_cpu_context(ctx);

	cpuctx = __get_cpu_context(ctx);





	/* Only set/clear cpuctx->cgrp if current task uses event->cgrp. */

	if (perf_cgroup_from_task(current, ctx) != event->cgrp) {

	/*

	/*

		 * We are removing the last cpu event in this context.

	 * cpuctx->cgrp is NULL until a cgroup event is sched in or

		 * If that event is not active in this cpu, cpuctx->cgrp

	 * ctx->nr_cgroup == 0 .

		 * should've been cleared by perf_cgroup_switch.

	 */

	 */

		WARN_ON_ONCE(!add && cpuctx->cgrp);

	if (add && perf_cgroup_from_task(current, ctx) == event->cgrp)

		return;

		cpuctx->cgrp = event->cgrp;

	}

	else if (!add)

	cpuctx->cgrp = add ? event->cgrp : NULL;

		cpuctx->cgrp = NULL;

}

}





#else /* !CONFIG_CGROUP_PERF */

#else /* !CONFIG_CGROUP_PERF */