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Commit bf762276 authored by Patrick Daly's avatar Patrick Daly
Browse files

iommu: io-pgtable-arm: Implement IOMMU_USE_UPSTREAM_HINT 



Set the appropriate MAIR to to use the bus attributes from the upstream
device, rather than override them in the SMMU. This feature requires
special iommu hw support and will be activated if the SMMU sets a 'magic'
MAIR attribute.

The MAIR attribute requirements are:
Inner Cacheablity = 0
Outer Cacheablity = 1, Write-Back Write Allocate
Outer Shareablity = 1

Change-Id: I3610fd94cd41cc94b2db870c30a7ce996ca02301
Signed-off-by: default avatarPatrick Daly <pdaly@codeaurora.org>
parent d4c72c41

drivers/iommu/io-pgtable-arm.c

+8 −1
Original line number Diff line number Diff line
@@ -165,9 +165,11 @@ 
#define ARM_LPAE_MAIR_ATTR_DEVICE	0x04

#define ARM_LPAE_MAIR_ATTR_NC		0x44

#define ARM_LPAE_MAIR_ATTR_WBRWA	0xff

#define ARM_LPAE_MAIR_ATTR_UPSTREAM	0xf4

#define ARM_LPAE_MAIR_ATTR_IDX_NC	0

#define ARM_LPAE_MAIR_ATTR_IDX_CACHE	1

#define ARM_LPAE_MAIR_ATTR_IDX_DEV	2

#define ARM_LPAE_MAIR_ATTR_IDX_UPSTREAM	3



/* IOPTE accessors */

#define iopte_deref(pte, d)						\
@@ -483,6 +485,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, 
		else if (prot & IOMMU_CACHE)

			pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE

				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);

		else if (prot & IOMMU_USE_UPSTREAM_HINT)

			pte |= (ARM_LPAE_MAIR_ATTR_IDX_UPSTREAM

				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);

	} else {

		pte = ARM_LPAE_PTE_HAP_FAULT;

		if (prot & IOMMU_READ)
@@ -985,7 +990,9 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) 
	      (ARM_LPAE_MAIR_ATTR_WBRWA

	       << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |

	      (ARM_LPAE_MAIR_ATTR_DEVICE

	       << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));

	       << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV)) |

	      (ARM_LPAE_MAIR_ATTR_UPSTREAM

	       << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_UPSTREAM));



	cfg->arm_lpae_s1_cfg.mair[0] = reg;

	cfg->arm_lpae_s1_cfg.mair[1] = 0;

drivers/iommu/io-pgtable-fast.c

+8 −1
Original line number Diff line number Diff line
@@ -133,9 +133,11 @@ struct av8l_fast_io_pgtable { 
#define AV8L_FAST_MAIR_ATTR_DEVICE	0x04

#define AV8L_FAST_MAIR_ATTR_NC		0x44

#define AV8L_FAST_MAIR_ATTR_WBRWA	0xff

#define AV8L_FAST_MAIR_ATTR_UPSTREAM	0xf4

#define AV8L_FAST_MAIR_ATTR_IDX_NC	0

#define AV8L_FAST_MAIR_ATTR_IDX_CACHE	1

#define AV8L_FAST_MAIR_ATTR_IDX_DEV	2

#define AV8L_FAST_MAIR_ATTR_IDX_UPSTREAM	3



#define AV8L_FAST_PAGE_SHIFT		12
@@ -204,6 +206,9 @@ int av8l_fast_map_public(av8l_fast_iopte *ptep, phys_addr_t paddr, size_t size, 
	else if (prot & IOMMU_CACHE)

		pte |= (AV8L_FAST_MAIR_ATTR_IDX_CACHE

			<< AV8L_FAST_PTE_ATTRINDX_SHIFT);

	else if (prot & IOMMU_USE_UPSTREAM_HINT)

		pte |= (AV8L_FAST_MAIR_ATTR_IDX_UPSTREAM

			<< AV8L_FAST_PTE_ATTRINDX_SHIFT);



	if (!(prot & IOMMU_WRITE))

		pte |= AV8L_FAST_PTE_AP_RO;
@@ -467,7 +472,9 @@ av8l_fast_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie) 
	      (AV8L_FAST_MAIR_ATTR_WBRWA

	       << AV8L_FAST_MAIR_ATTR_SHIFT(AV8L_FAST_MAIR_ATTR_IDX_CACHE)) |

	      (AV8L_FAST_MAIR_ATTR_DEVICE

	       << AV8L_FAST_MAIR_ATTR_SHIFT(AV8L_FAST_MAIR_ATTR_IDX_DEV));

	       << AV8L_FAST_MAIR_ATTR_SHIFT(AV8L_FAST_MAIR_ATTR_IDX_DEV)) |

	      (AV8L_FAST_MAIR_ATTR_UPSTREAM

	       << AV8L_FAST_MAIR_ATTR_SHIFT(AV8L_FAST_MAIR_ATTR_IDX_UPSTREAM));



	cfg->av8l_fast_cfg.mair[0] = reg;

	cfg->av8l_fast_cfg.mair[1] = 0;