staging: rtl8712: checkpatch cleanup: block comments using a trailing */ (bef611a9) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/staging/rtl8712/rtl8712_led.c

+8 −4

Original line number	Diff line number	Diff line
		@@ -58,10 +58,12 @@ enum _LED_STATE_871x {
		LED_POWER_ON_BLINK = 5,
		LED_SCAN_BLINK = 6, /* LED is blinking during scanning period,
		* the # of times to blink is depend on time
		* for scanning. */
		* for scanning.
		*/
		LED_NO_LINK_BLINK = 7, /* LED is blinking during no link state. */
		LED_BLINK_StartToBlink = 8,/* Customized for Sercomm Printer
		* Server case */
		* Server case
		*/
		LED_BLINK_WPS = 9, /* LED is blinkg during WPS communication */
		LED_TXRX_BLINK = 10,
		LED_BLINK_WPS_STOP = 11, /for ALPHA /
		@@ -110,7 +112,8 @@ static void DeInitLed871x(struct LED_871x *pLed)
		{
		del_timer_sync(&pLed->BlinkTimer);
		/* We should reset bLedBlinkInProgress if we cancel
		* the LedControlTimer, */
		* the LedControlTimer,
		*/
		pLed->bLedBlinkInProgress = false;
		}

		@@ -827,7 +830,8 @@ static void BlinkTimerCallback(unsigned long data)
		struct LED_871x pLed = (struct LED_871x )data;

		/* This fixed the crash problem on Fedora 12 when trying to do the
		* insmod;ifconfig up;rmmod commands. */
		* insmod;ifconfig up;rmmod commands.
		*/
		if (pLed->padapter->bSurpriseRemoved \|\| pLed->padapter->bDriverStopped)
		return;
		schedule_work(&pLed->BlinkWorkItem);

drivers/staging/rtl8712/rtl8712_recv.c

+36 −18

Original line number	Diff line number	Diff line
		@@ -163,7 +163,8 @@ static void update_recvframe_attrib_from_recvstat(struct rx_pkt_attrib *pattrib,
		drvinfo_sz = (le32_to_cpu(prxstat->rxdw0) & 0x000f0000) >> 16;
		drvinfo_sz <<= 3;
		/*TODO:
		* Offset 0 */
		* Offset 0
		*/
		pattrib->bdecrypted = ((le32_to_cpu(prxstat->rxdw0) & BIT(27)) >> 27)
		? 0 : 1;
		pattrib->crc_err = (le32_to_cpu(prxstat->rxdw0) & BIT(14)) >> 14;
		@@ -210,7 +211,8 @@ static union recv_frame recvframe_defrag(struct _adapter adapter,
		curfragnum = 0;
		if (curfragnum != pfhdr->attrib.frag_num) {
		/*the first fragment number must be 0
		free the whole queue/
		*free the whole queue
		*/
		r8712_free_recvframe(prframe, pfree_recv_queue);
		r8712_free_recvframe_queue(defrag_q, pfree_recv_queue);
		return NULL;
		@@ -224,18 +226,21 @@ static union recv_frame recvframe_defrag(struct _adapter adapter,
		/check the fragment sequence (2nd ~n fragment frame) /
		if (curfragnum != pnfhdr->attrib.frag_num) {
		/* the fragment number must increase (after decache)
		* release the defrag_q & prframe */
		* release the defrag_q & prframe
		*/
		r8712_free_recvframe(prframe, pfree_recv_queue);
		r8712_free_recvframe_queue(defrag_q, pfree_recv_queue);
		return NULL;
		}
		curfragnum++;
		/* copy the 2nd~n fragment frame's payload to the first fragment
		* get the 2nd~last fragment frame's payload */
		* get the 2nd~last fragment frame's payload
		*/
		wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len;
		recvframe_pull(pnextrframe, wlanhdr_offset);
		/* append to first fragment frame's tail (if privacy frame,
		* pull the ICV) */
		* pull the ICV)
		*/
		recvframe_pull_tail(prframe, pfhdr->attrib.icv_len);
		memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len);
		recvframe_put(prframe, pnfhdr->len);
		@@ -278,7 +283,8 @@ union recv_frame r8712_recvframe_chk_defrag(struct _adapter padapter,
		prtnframe = precv_frame;/isn't a fragment frame/
		if (ismfrag == 1) {
		/* 0~(n-1) fragment frame
		* enqueue to defraf_g */
		* enqueue to defraf_g
		*/
		if (pdefrag_q != NULL) {
		if (fragnum == 0) {
		/the first fragment/
		@@ -294,7 +300,8 @@ union recv_frame r8712_recvframe_chk_defrag(struct _adapter padapter,
		prtnframe = NULL;
		} else {
		/* can't find this ta's defrag_queue, so free this
		* recv_frame */
		* recv_frame
		*/
		r8712_free_recvframe(precv_frame, pfree_recv_queue);
		prtnframe = NULL;
		}
		@@ -302,7 +309,8 @@ union recv_frame r8712_recvframe_chk_defrag(struct _adapter padapter,
		}
		if ((ismfrag == 0) && (fragnum != 0)) {
		/* the last fragment frame
		* enqueue the last fragment */
		* enqueue the last fragment
		*/
		if (pdefrag_q != NULL) {
		phead = &pdefrag_q->queue;
		list_add_tail(&pfhdr->list, phead);
		@@ -311,7 +319,8 @@ union recv_frame r8712_recvframe_chk_defrag(struct _adapter padapter,
		prtnframe = precv_frame;
		} else {
		/* can't find this ta's defrag_queue, so free this
		* recv_frame */
		* recv_frame
		*/
		r8712_free_recvframe(precv_frame, pfree_recv_queue);
		prtnframe = NULL;
		}
		@@ -391,7 +400,8 @@ static int amsdu_to_msdu(struct _adapter padapter, union recv_frame prframe)
		eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) \|\|
		!memcmp(sub_skb->data, bridge_tunnel_header, SNAP_SIZE))) {
		/* remove RFC1042 or Bridge-Tunnel encapsulation and
		* replace EtherType */
		* replace EtherType
		*/
		skb_pull(sub_skb, SNAP_SIZE);
		memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src,
		ETH_ALEN);
		@@ -530,7 +540,8 @@ int r8712_recv_indicatepkts_in_order(struct _adapter *padapter,
		preorder_ctrl->indicate_seq = pattrib->seq_num;
		}
		/* Prepare indication list and indication.
		* Check if there is any packet need indicate. */
		* Check if there is any packet need indicate.
		*/
		while (!list_empty(phead)) {
		prframe = container_of(plist, union recv_frame, u.list);
		pattrib = &prframe->u.hdr.attrib;
		@@ -757,7 +768,8 @@ static void query_rx_phy_status(struct _adapter *padapter,
		/* Modify the RF RNA gain value to -40, -20,
		* -2, 14 by Jenyu's suggestion
		* Note: different RF with the different
		* RNA gain. */
		* RNA gain.
		*/
		case 0x3:
		rx_pwr_all = -40 - (pcck_buf->cck_agc_rpt &
		0x3e);
		@@ -842,7 +854,8 @@ static void query_rx_phy_status(struct _adapter *padapter,
		total_rssi += rssi;
		}
		/* (2)PWDB, Average PWDB cacluated by hardware (for
		* rate adaptive) */
		* rate adaptive)
		*/
		rx_pwr_all = (((pphy_head[PHY_STAT_PWDB_ALL_SHT]) >> 1) & 0x7f)
		- 106;
		pwdb_all = query_rx_pwr_percentage(rx_pwr_all);
		@@ -870,7 +883,8 @@ static void query_rx_phy_status(struct _adapter *padapter,
		}
		/* UI BSS List signal strength(in percentage), make it good looking,
		* from 0~100. It is assigned to the BSS List in
		* GetValueFromBeaconOrProbeRsp(). */
		* GetValueFromBeaconOrProbeRsp().
		*/
		if (bcck_rate)
		prframe->u.hdr.attrib.signal_strength =
		(u8)r8712_signal_scale_mapping(pwdb_all);
		@@ -1027,10 +1041,12 @@ static int recvbuf2recvframe(struct _adapter padapter, struct sk_buff pskb)
		transfer_len = pskb->len;
		/* Test throughput with Netgear 3700 (No security) with Chariot 3T3R
		* pairs. The packet count will be a big number so that the containing
		* packet will effect the Rx reordering. */
		* packet will effect the Rx reordering.
		*/
		if (transfer_len < pkt_len) {
		/* In this case, it means the MAX_RECVBUF_SZ is too small to
		* get the data from 8712u. */
		* get the data from 8712u.
		*/
		return _FAIL;
		}
		do {
		@@ -1057,14 +1073,16 @@ static int recvbuf2recvframe(struct _adapter padapter, struct sk_buff pskb)
		tmp_len = pkt_len + drvinfo_sz + RXDESC_SIZE;
		pkt_offset = (u16)round_up(tmp_len, 128);
		/* for first fragment packet, driver need allocate 1536 +
		* drvinfo_sz + RXDESC_SIZE to defrag packet. */
		* drvinfo_sz + RXDESC_SIZE to defrag packet.
		*/
		if ((mf == 1) && (frag == 0))
		/1658+6=1664, 1664 is 128 alignment./
		alloc_sz = max_t(u16, tmp_len, 1658);
		else
		alloc_sz = tmp_len;
		/* 2 is for IP header 4 bytes alignment in QoS packet case.
		* 4 is for skb->data 4 bytes alignment. */
		* 4 is for skb->data 4 bytes alignment.
		*/
		alloc_sz += 6;
		pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz);
		if (pkt_copy) {

drivers/staging/rtl8712/rtl8712_recv.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -61,7 +61,8 @@ struct recv_stat {
		struct phy_cck_rx_status {
		/* For CCK rate descriptor. This is a unsigned 8:1 variable.
		* LSB bit present 0.5. And MSB 7 bts present a signed value.
		* Range from -64~+63.5. */
		* Range from -64~+63.5.
		*/
		u8 adc_pwdb_X[4];
		u8 sq_rpt;
		u8 cck_agc_rpt;

drivers/staging/rtl8712/rtl8712_spec.h

+2 −1

Original line number	Diff line number	Diff line
		@@ -83,7 +83,8 @@

		#define CMD_ADDR_MAPPING_SHIFT 2 /*SDIO CMD ADDR MAPPING,
		*shift 2 bit for match
		* offset[14:2]*/
		* offset[14:2]
		*/

		/Offset for SDIO LOCAL/
		#define OFFSET_SDIO_LOCAL 0x0FFF

drivers/staging/rtl8712/rtl8712_syscfg_bitdef.h

+18 −9

Original line number	Diff line number	Diff line
		@@ -68,11 +68,13 @@
		#define SYS_CLKSEL BIT(SYS_CLKSEL_SHT) /* System Clock 80MHz*/
		#define PS_CLKSEL_SHT 1
		#define PS_CLKSEL BIT(PS_CLKSEL_SHT) /*System power save
		* clock select.*/
		* clock select.
		*/
		#define CPU_CLKSEL_SHT 2
		#define CPU_CLKSEL BIT(CPU_CLKSEL_SHT) /* System Clock select,
		* 1: AFE source,
		* 0: System clock(L-Bus)*/
		* 0: System clock(L-Bus)
		*/
		#define INT32K_EN_SHT 3
		#define INT32K_EN BIT(INT32K_EN_SHT)
		#define MACSLP_SHT 4
		@@ -85,10 +87,12 @@
		#define RING_CLK_EN BIT(RING_CLK_EN_SHT)
		#define SWHW_SEL_SHT 14
		#define SWHW_SEL BIT(SWHW_SEL_SHT) /* Load done,
		* control path switch.*/
		* control path switch.
		*/
		#define FWHW_SEL_SHT 15
		#define FWHW_SEL BIT(FWHW_SEL_SHT) /* Sleep exit,
		* control path switch.*/
		* control path switch.
		*/

		/9346CR/
		#define _VPDIDX_MSK 0xFF00
		@@ -118,10 +122,12 @@
		#define AFE_MISC_E32_EN BIT(AFE_MISC_E32_EN_SHT)
		#define AFE_MISC_MBEN_SHT 1
		#define AFE_MISC_MBEN BIT(AFE_MISC_MBEN_SHT)/* Enable AFE Macro
		* Block's Mbias.*/
		* Block's Mbias.
		*/
		#define AFE_MISC_BGEN_SHT 0
		#define AFE_MISC_BGEN BIT(AFE_MISC_BGEN_SHT)/* Enable AFE Macro
		* Block's Bandgap.*/
		* Block's Bandgap.
		*/


		/--------------------------------------------------------------------------/
		@@ -149,10 +155,12 @@

		/* EFUSE_CTRL*/
		#define EF_FLAG BIT(31) /* Access Flag, Write:1;
		* Read:0*/
		* Read:0
		*/
		#define EF_PGPD 0x70000000 /* E-fuse Program time*/
		#define EF_RDT 0x0F000000 /* E-fuse read time: in the
		* unit of cycle time*/
		* unit of cycle time
		*/
		#define EF_PDN_EN BIT(19) /* EFuse Power down enable*/
		#define ALD_EN BIT(18) /* Autoload Enable*/
		#define EF_ADDR 0x0003FF00 /* Access Address*/
		@@ -164,7 +172,8 @@
		/* EFUSE_CLK_CTRL*/
		#define EFUSE_CLK_EN BIT(1) /* E-Fuse Clock Enable*/
		#define EFUSE_CLK_SEL BIT(0) /* E-Fuse Clock Select,
		* 0:500K, 1:40M*/
		* 0:500K, 1:40M
		*/

		#endif /__RTL8712_SYSCFG_BITDEF_H__/