Merge "ARM: dts: msm: Add GPU coresight properties for SDM845" (bea75a96) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/devicetree/bindings/gpu/adreno.txt

+10 −7

Original line number	Diff line number	Diff line
		@@ -211,19 +211,22 @@ GPU LLC slice info:
		and pagetable walk.
		- cache-slices: phandle to the system LLC driver, cache slice index.


		GPU coresight info:
		The following properties are optional as collecting data via coresight might
		not be supported for every chipset. The documentation for coresight
		properties can be found in:
		Documentation/devicetree/bindings/coresight/coresight.txt

		- coresight-id Unique integer identifier for the bus.
		- coresight-name Unique descriptive name of the bus.
		- coresight-nr-inports Number of input ports on the bus.
		- coresight-outports List of output port numbers on the bus.
		- coresight-child-list List of phandles pointing to the children of this
		- qcom,gpu-coresights: Container for sets of GPU coresight sources.
		- coresight-id: Unique integer identifier for the bus.
		- coresight-name: Unique descriptive name of the bus.
		- coresight-nr-inports: Number of input ports on the bus.
		- coresight-outports: List of output port numbers on the bus.
		- coresight-child-list: List of phandles pointing to the children of this
		component.
		- coresight-child-ports List of input port numbers of the children.
		- coresight-atid The unique ATID value of the coresight device
		- coresight-child-ports: List of input port numbers of the children.
		- coresight-atid: The unique ATID value of the coresight device

		Example of A330 GPU in MSM8916:

+52 −0

Original line number	Diff line number	Diff line
		@@ -522,6 +522,58 @@
		};
		};

		port@5 {
		reg = <6>;
		funnel_in2_in_funnel_gfx: endpoint {
		slave-mode;
		remote-endpoint =
		<&funnel_gfx_out_funnel_in2>;
		};
		};
		};
		};

		funnel_gfx: funnel@0x6943000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6943000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-gfx";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		funnel_gfx_out_funnel_in2: endpoint {
		remote-endpoint =
		<&funnel_in2_in_funnel_gfx>;
		};
		};

		port@1 {
		reg = <0>;
		funnel_in2_in_gfx: endpoint {
		slave-mode;
		remote-endpoint =
		<&gfx_out_funnel_in2>;
		};
		};

		port@2 {
		reg = <1>;
		funnel_in2_in_gfx_cx: endpoint {
		slave-mode;
		remote-endpoint =
		<&gfx_cx_out_funnel_in2>;
		};
		};
		};
		};

+30 −0

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		@@ -122,6 +122,36 @@
		cache-slice-names = "gpu", "gpuhtw";
		cache-slices = <&llcc 12>, <&llcc 11>;

		qcom,gpu-coresights {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "qcom,gpu-coresight";

		qcom,gpu-coresight@0 {
		reg = <0>;
		coresight-name = "coresight-gfx";
		coresight-atid = <50>;
		port {
		gfx_out_funnel_in2: endpoint {
		remote-endpoint =
		<&funnel_in2_in_gfx>;
		};
		};
		};

		qcom,gpu-coresight@1 {
		reg = <1>;
		coresight-name = "coresight-gfx-cx";
		coresight-atid = <51>;
		port {
		gfx_cx_out_funnel_in2: endpoint {
		remote-endpoint =
		<&funnel_in2_in_gfx_cx>;
		};
		};
		};
		};

		/* GPU Mempools */
		qcom,gpu-mempools {
		#address-cells = <1>;