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Commit be7f2615 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0/gr: update fuc source to assemble with latest envyas 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 020c6bf3

drivers/gpu/drm/nouveau/nvc0_graph.fuc

+28 −28
Original line number Diff line number Diff line
@@ -71,9 +71,9 @@ queue_put: 
	ld b32 $r9 D[$r13 + 0x4]	// PUT

	xor $r8 8

	cmpu b32 $r8 $r9

	bra ne queue_put_next

	bra ne #queue_put_next

		mov $r15 E_CMD_OVERFLOW

		call error

		call #error

		ret



	// store cmd/data on queue
@@ -104,7 +104,7 @@ queue_get: 
	ld b32 $r8 D[$r13 + 0x0]	// GET

	ld b32 $r9 D[$r13 + 0x4]	// PUT

	cmpu b32 $r8 $r9

	bra e queue_get_done

	bra e #queue_get_done

		// fetch first cmd/data pair

		and $r9 $r8 7

		shl b32 $r9 3
@@ -135,9 +135,9 @@ nv_rd32: 
	nv_rd32_wait:

		iord $r12 I[$r11 + 0x000]

		xbit $r12 $r12 31

		bra ne nv_rd32_wait

		bra ne #nv_rd32_wait

	mov $r10 6			// DONE_MMIO_RD

	call wait_doneo

	call #wait_doneo

	iord $r15 I[$r11 + 0x100]	// MMIO_RDVAL

	ret
@@ -157,7 +157,7 @@ nv_wr32: 
	nv_wr32_wait:

		iord $r12 I[$r11 + 0x000]

		xbit $r12 $r12 31

		bra ne nv_wr32_wait

		bra ne #nv_wr32_wait

	ret



// (re)set watchdog timer
@@ -193,7 +193,7 @@ $1: 
		shl b32 $r8 6

		iord $r8 I[$r8 + 0x000]	// DONE

		xbit $r8 $r8 $r10

		bra $2 wait_done_$1

		bra $2 #wait_done_$1

	trace_clr(T_WAIT)

	ret

')
@@ -216,7 +216,7 @@ mmctx_size: 
		add b32 $r9 $r8

		add b32 $r14 4

		cmpu b32 $r14 $r15

		bra ne nv_mmctx_size_loop

		bra ne #nv_mmctx_size_loop

	mov b32 $r15 $r9

	ret
@@ -238,12 +238,12 @@ mmctx_xfer: 
	shl b32 $r8 6

	clear b32 $r9

	or $r11 $r11

	bra e mmctx_base_disabled

	bra e #mmctx_base_disabled

		iowr I[$r8 + 0x000] $r11	// MMCTX_BASE

		bset $r9 0			// BASE_EN

	mmctx_base_disabled:

	or $r14 $r14

	bra e mmctx_multi_disabled

	bra e #mmctx_multi_disabled

		iowr I[$r8 + 0x200] $r14 	// MMCTX_MULTI_STRIDE

		iowr I[$r8 + 0x300] $r15 	// MMCTX_MULTI_MASK

		bset $r9 1			// MULTI_EN
@@ -264,7 +264,7 @@ mmctx_xfer: 
		mmctx_wait_free:

			iord $r14 I[$r8 + 0x000] // MMCTX_CTRL

			and $r14 0x1f

			bra e mmctx_wait_free

			bra e #mmctx_wait_free



		// queue up an entry

		ld b32 $r14 D[$r12]
@@ -272,19 +272,19 @@ mmctx_xfer: 
		iowr I[$r8 + 0x300] $r14

		add b32 $r12 4

		cmpu b32 $r12 $r13

		bra ne mmctx_exec_loop

		bra ne #mmctx_exec_loop



	xbit $r11 $r10 2

	bra ne mmctx_stop

	bra ne #mmctx_stop

		// wait for queue to empty

		mmctx_fini_wait:

			iord $r11 I[$r8 + 0x000]	// MMCTX_CTRL

			and $r11 0x1f

			cmpu b32 $r11 0x10

			bra ne mmctx_fini_wait

			bra ne #mmctx_fini_wait

		mov $r10 2				// DONE_MMCTX

		call wait_donez

		bra mmctx_done

		call #wait_donez

		bra #mmctx_done

	mmctx_stop:

		xbit $r11 $r10 0

		shl b32 $r11 16			// DIR
@@ -295,7 +295,7 @@ mmctx_xfer: 
			// wait for STOP_TRIGGER to clear

			iord $r11 I[$r8 + 0x000] // MMCTX_CTRL

			xbit $r11 $r11 18

			bra ne mmctx_stop_wait

			bra ne #mmctx_stop_wait

	mmctx_done:

	trace_clr(T_MMCTX)

	ret
@@ -305,7 +305,7 @@ mmctx_xfer: 
strand_wait:

	push $r10

	mov $r10 2

	call wait_donez

	call #wait_donez

	pop $r10

	ret
@@ -316,7 +316,7 @@ strand_pre: 
	sethi $r8 0x20000

	mov $r9 0xc

	iowr I[$r8] $r9

	call strand_wait

	call #strand_wait

	ret



// unknown - call after issuing strand commands
@@ -326,7 +326,7 @@ strand_post: 
	sethi $r8 0x20000

	mov $r9 0xd

	iowr I[$r8] $r9

	call strand_wait

	call #strand_wait

	ret



// Selects strand set?!
@@ -341,11 +341,11 @@ strand_set: 
	iowr I[$r10 + 0x000] $r12		// 0x93c = 0xf

	mov $r12 0xb

	iowr I[$r11 + 0x000] $r12		// 0x928 = 0xb

	call strand_wait

	call #strand_wait

	iowr I[$r10 + 0x000] $r14		// 0x93c = <id>

	mov $r12 0xa

	iowr I[$r11 + 0x000] $r12		// 0x928 = 0xa

	call strand_wait

	call #strand_wait

	ret



// Initialise strand context data
@@ -357,22 +357,22 @@ strand_set: 
//

strand_ctx_init:

	trace_set(T_STRINIT)

	call strand_pre

	call #strand_pre

	mov $r14 3

	call strand_set

	call #strand_set

	mov $r10 0x46fc

	sethi $r10 0x20000

	add b32 $r11 $r10 0x400

	iowr I[$r10 + 0x100] $r0	// STRAND_FIRST_GENE = 0

	mov $r12 1

	iowr I[$r11 + 0x000] $r12	// STRAND_CMD = LATCH_FIRST_GENE

	call strand_wait

	call #strand_wait

	sub b32 $r12 $r0 1

	iowr I[$r10 + 0x000] $r12	// STRAND_GENE_CNT = 0xffffffff

	mov $r12 2

	iowr I[$r11 + 0x000] $r12	// STRAND_CMD = LATCH_GENE_CNT

	call strand_wait

	call strand_post

	call #strand_wait

	call #strand_post



	// read the size of each strand, poke the context offset of

	// each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
@@ -391,7 +391,7 @@ strand_ctx_init: 
		add b32 $r14 $r10

		add b32 $r8 4

		sub b32 $r9 1

		bra ne ctx_init_strand_loop

		bra ne #ctx_init_strand_loop



	shl b32 $r14 8

	sub b32 $r15 $r14 $r15

drivers/gpu/drm/nouveau/nvc0_grgpc.fuc

+79 −79
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
 * - watchdog timer around ctx operations

 */



.section nvc0_grgpc_data

.section #nvc0_grgpc_data

include(`nvc0_graph.fuc')

gpc_id:			.b32 0

gpc_mmio_list_head:	.b32 0
@@ -48,40 +48,40 @@ cmd_queue: queue_init 
// chipset descriptions

chipsets:

.b8  0xc0 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc0_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc0_tpc_mmio_tail

.b8  0xc1 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc1_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc1_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc1_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc1_tpc_mmio_tail

.b8  0xc3 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc3_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc3_tpc_mmio_tail

.b8  0xc4 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc3_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc3_tpc_mmio_tail

.b8  0xc8 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc0_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc0_tpc_mmio_tail

.b8  0xce 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvc3_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvc3_tpc_mmio_tail

.b8  0xcf 0 0 0

.b16 nvc0_gpc_mmio_head

.b16 nvc0_gpc_mmio_tail

.b16 nvc0_tpc_mmio_head

.b16 nvcf_tpc_mmio_tail

.b16 #nvc0_gpc_mmio_head

.b16 #nvc0_gpc_mmio_tail

.b16 #nvc0_tpc_mmio_head

.b16 #nvcf_tpc_mmio_tail

.b8  0 0 0 0



// GPC mmio lists
@@ -147,8 +147,8 @@ mmctx_data(0x000544, 1) 
nvc1_tpc_mmio_tail:





.section nvc0_grgpc_code

bra init

.section #nvc0_grgpc_code

bra #init

define(`include_code')

include(`nvc0_graph.fuc')
@@ -160,10 +160,10 @@ error: 
	push $r14

	mov $r14 -0x67ec 	// 0x9814

	sethi $r14 0x400000

	call nv_wr32		// HUB_CTXCTL_CC_SCRATCH[5] = error code

	call #nv_wr32		// HUB_CTXCTL_CC_SCRATCH[5] = error code

	add b32 $r14 0x41c

	mov $r15 1

	call nv_wr32		// HUB_CTXCTL_INTR_UP_SET

	call #nv_wr32		// HUB_CTXCTL_INTR_UP_SET

	pop $r14

	ret
@@ -190,7 +190,7 @@ init: 
	iowr I[$r1 + 0x000] $r2		// FIFO_ENABLE



	// setup i0 handler, and route all interrupts to it

	mov $r1 ih

	mov $r1 #ih

	mov $iv0 $r1

	mov $r1 0x400

	iowr I[$r1 + 0x300] $r0		// INTR_DISPATCH
@@ -210,24 +210,24 @@ init: 
	and $r2 0x1f

	shl b32 $r3 $r2

	sub b32 $r3 1

	st b32 D[$r0 + tpc_count] $r2

	st b32 D[$r0 + tpc_mask] $r3

	st b32 D[$r0 + #tpc_count] $r2

	st b32 D[$r0 + #tpc_mask] $r3

	add b32 $r1 0x400

	iord $r2 I[$r1 + 0x000]		// MYINDEX

	st b32 D[$r0 + gpc_id] $r2

	st b32 D[$r0 + #gpc_id] $r2



	// find context data for this chipset

	mov $r2 0x800

	shl b32 $r2 6

	iord $r2 I[$r2 + 0x000]		// CC_SCRATCH[0]

	mov $r1 chipsets - 12

	mov $r1 #chipsets - 12

	init_find_chipset:

		add b32 $r1 12

		ld b32 $r3 D[$r1 + 0x00]

		cmpu b32 $r3 $r2

		bra e init_context

		bra e #init_context

		cmpu b32 $r3 0

		bra ne init_find_chipset

		bra ne #init_find_chipset

		// unknown chipset

		ret
@@ -253,19 +253,19 @@ init: 
	clear b32 $r15

	ld b16 $r14 D[$r1 + 4]

	ld b16 $r15 D[$r1 + 6]

	st b16 D[$r0 + gpc_mmio_list_head] $r14

	st b16 D[$r0 + gpc_mmio_list_tail] $r15

	call mmctx_size

	st b16 D[$r0 + #gpc_mmio_list_head] $r14

	st b16 D[$r0 + #gpc_mmio_list_tail] $r15

	call #mmctx_size

	add b32 $r2 $r15

	add b32 $r3 $r15



	// calculate per-TPC mmio context size, store the list pointers

	ld b16 $r14 D[$r1 + 8]

	ld b16 $r15 D[$r1 + 10]

	st b16 D[$r0 + tpc_mmio_list_head] $r14

	st b16 D[$r0 + tpc_mmio_list_tail] $r15

	call mmctx_size

	ld b32 $r14 D[$r0 + tpc_count]

	st b16 D[$r0 + #tpc_mmio_list_head] $r14

	st b16 D[$r0 + #tpc_mmio_list_tail] $r15

	call #mmctx_size

	ld b32 $r14 D[$r0 + #tpc_count]

	mulu $r14 $r15

	add b32 $r2 $r14

	add b32 $r3 $r14
@@ -283,7 +283,7 @@ init: 


	// calculate size of strand context data

	mov b32 $r15 $r2

	call strand_ctx_init

	call #strand_ctx_init

	add b32 $r3 $r15



	// save context size, and tell HUB we're done
@@ -301,13 +301,13 @@ init: 
main:

	bset $flags $p0

	sleep $p0

	mov $r13 cmd_queue

	call queue_get

	bra $p1 main

	mov $r13 #cmd_queue

	call #queue_get

	bra $p1 #main



	// 0x0000-0x0003 are all context transfers

	cmpu b32 $r14 0x04

	bra nc main_not_ctx_xfer

	bra nc #main_not_ctx_xfer

		// fetch $flags and mask off $p1/$p2

		mov $r1 $flags

		mov $r2 0x0006
@@ -318,14 +318,14 @@ main: 
		or $r1 $r14

		mov $flags $r1

		// transfer context data

		call ctx_xfer

		bra main

		call #ctx_xfer

		bra #main



	main_not_ctx_xfer:

	shl b32 $r15 $r14 16

	or $r15 E_BAD_COMMAND

	call error

	bra main

	call #error

	bra #main



// interrupt handler

ih:
@@ -342,13 +342,13 @@ ih: 
	// incoming fifo command?

	iord $r10 I[$r0 + 0x200]	// INTR

	and $r11 $r10 0x00000004

	bra e ih_no_fifo

	bra e #ih_no_fifo

		// queue incoming fifo command for later processing

		mov $r11 0x1900

		mov $r13 cmd_queue

		mov $r13 #cmd_queue

		iord $r14 I[$r11 + 0x100]	// FIFO_CMD

		iord $r15 I[$r11 + 0x000]	// FIFO_DATA

		call queue_put

		call #queue_put

		add b32 $r11 0x400

		mov $r14 1

		iowr I[$r11 + 0x000] $r14	// FIFO_ACK
@@ -374,11 +374,11 @@ ih: 
//

hub_barrier_done:

	mov $r15 1

	ld b32 $r14 D[$r0 + gpc_id]

	ld b32 $r14 D[$r0 + #gpc_id]

	shl b32 $r15 $r14

	mov $r14 -0x6be8 	// 0x409418 - HUB_BAR_SET

	sethi $r14 0x400000

	call nv_wr32

	call #nv_wr32

	ret



// Disables various things, waits a bit, and re-enables them..
@@ -395,7 +395,7 @@ ctx_redswitch: 
	mov $r15 8

	ctx_redswitch_delay:

		sub b32 $r15 1

		bra ne ctx_redswitch_delay

		bra ne #ctx_redswitch_delay

	mov $r15 0xa20

	iowr I[$r14] $r15	// GPC_RED_SWITCH = UNK11, ENABLE, POWER

	ret
@@ -413,8 +413,8 @@ ctx_xfer: 
	mov $r1 0xa04

	shl b32 $r1 6

	iowr I[$r1 + 0x000] $r15// MEM_BASE

	bra not $p1 ctx_xfer_not_load

		call ctx_redswitch

	bra not $p1 #ctx_xfer_not_load

		call #ctx_redswitch

	ctx_xfer_not_load:



	// strands
@@ -422,7 +422,7 @@ ctx_xfer: 
	sethi $r1 0x20000

	mov $r2 0xc

	iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0c

	call strand_wait

	call #strand_wait

	mov $r2 0x47fc

	sethi $r2 0x20000

	iowr I[$r2] $r0		// STRAND_FIRST_GENE(0x3f) = 0x00
@@ -435,46 +435,46 @@ ctx_xfer: 
	or $r10 2		// first

	mov $r11 0x0000

	sethi $r11 0x500000

	ld b32 $r12 D[$r0 + gpc_id]

	ld b32 $r12 D[$r0 + #gpc_id]

	shl b32 $r12 15

	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn

	ld b32 $r12 D[$r0 + gpc_mmio_list_head]

	ld b32 $r13 D[$r0 + gpc_mmio_list_tail]

	ld b32 $r12 D[$r0 + #gpc_mmio_list_head]

	ld b32 $r13 D[$r0 + #gpc_mmio_list_tail]

	mov $r14 0		// not multi

	call mmctx_xfer

	call #mmctx_xfer



	// per-TPC mmio context

	xbit $r10 $flags $p1	// direction

	or $r10 4		// last

	mov $r11 0x4000

	sethi $r11 0x500000	// base = NV_PGRAPH_GPC0_TPC0

	ld b32 $r12 D[$r0 + gpc_id]

	ld b32 $r12 D[$r0 + #gpc_id]

	shl b32 $r12 15

	add b32 $r11 $r12	// base = NV_PGRAPH_GPCn_TPC0

	ld b32 $r12 D[$r0 + tpc_mmio_list_head]

	ld b32 $r13 D[$r0 + tpc_mmio_list_tail]

	ld b32 $r15 D[$r0 + tpc_mask]

	ld b32 $r12 D[$r0 + #tpc_mmio_list_head]

	ld b32 $r13 D[$r0 + #tpc_mmio_list_tail]

	ld b32 $r15 D[$r0 + #tpc_mask]

	mov $r14 0x800		// stride = 0x800

	call mmctx_xfer

	call #mmctx_xfer



	// wait for strands to finish

	call strand_wait

	call #strand_wait



	// if load, or a save without a load following, do some

	// unknown stuff that's done after finishing a block of

	// strand commands

	bra $p1 ctx_xfer_post

	bra not $p2 ctx_xfer_done

	bra $p1 #ctx_xfer_post

	bra not $p2 #ctx_xfer_done

	ctx_xfer_post:

		mov $r1 0x4afc

		sethi $r1 0x20000

		mov $r2 0xd

		iowr I[$r1] $r2		// STRAND_CMD(0x3f) = 0x0d

		call strand_wait

		call #strand_wait



	// mark completion in HUB's barrier

	ctx_xfer_done:

	call hub_barrier_done

	call #hub_barrier_done

	ret



.align 256

drivers/gpu/drm/nouveau/nvc0_grhub.fuc

+133 −133

File changed.

Preview size limit exceeded, changes collapsed.