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Commit be6e3f31 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux into next/dt 

This pull request contains Device Tree changes for Broadcom ARM-based SoCs:

- Chris provides documentation and DTS fixes for the bcm11351 CPU enable-method in preparation
  for adding support for the BCM23550 SoC and its corresponding documentation, SoC dtsi
  and the Sparrow board DTS file

- Jon adds MSI support to the PCI nodes, updates the secondary cores boot address for the B0
  production revision of the Northstar Plus SoC, adds a DTS for the BCM958625HR board, another
  one for the BCM958525XMC board, and finally adds the PL330 DMA controller to the NSP DTS

- Rafal enables the SPI NOR flash on dual flash systems (NAND + SPI) on the BCM5301x SoCs
  and devices

- Florian adds support for the BCM5301x built-in Ethernet switch by adding nodes for the
  Gigabit MAC controllers and the Switch Register Access block, and finally updates the
  SmartRG SR-400AC board with its switch port layout

* tag 'arm-soc/for-4.8/devicetree' of http://github.com/Broadcom/stblinux

:
  ARM: dts: BCM5310x: Enable switch ports on SmartRG SR400AC
  ARM: dts: BCM5301X: Add SRAB interrupts
  ARM: dts: Enable SRAB switch and GMACs on 5301x DTS
  ARM: dts: NSP: Add PL330 support
  ARM: dts: NSP: Add XMC board support
  ARM: dts: bcm23550: Add device tree files
  Documentation: devicetree: Document BCM23550 bindings
  ARM: BCM5301X: Enable SPI-NOR on dual flash devices
  ARM: dts: NSP: Add new DT file for bcm958625hr
  ARM: dts: NSP: modify second CPU address
  ARM: dts: NSP: Add MSI support on PCI
  ARM: BCM: modify Broadcom CPU enable method
  ARM: dts: fix use of bcm11351 enable method
  Documentation: Binding docs for bcm11351 enable method

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 00d624dc 2df1808d

Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt

+3 −3
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs: 
  BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664



The enable method is specified by defining the following required

properties in the "cpus" device tree node:

properties in the "cpu" device tree node:

  - enable-method = "brcm,bcm11351-cpu-method";

  - secondary-boot-reg = <...>;
@@ -19,8 +19,6 @@ Example: 
	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		enable-method = "brcm,bcm11351-cpu-method";

		secondary-boot-reg = <0x3500417c>;



		cpu0: cpu@0 {

			device_type = "cpu";
@@ -32,5 +30,7 @@ Example: 
			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "brcm,bcm11351-cpu-method";

			secondary-boot-reg = <0x3500417c>;

		};

	};

Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt

0 → 100644
+36 −0
Original line number Diff line number Diff line 
Broadcom Kona Family CPU Enable Method

--------------------------------------

This binding defines the enable method used for starting secondary

CPUs in the following Broadcom SoCs:

  BCM23550



The enable method is specified by defining the following required

properties in the "cpu" device tree node:

  - enable-method = "brcm,bcm23550";

  - secondary-boot-reg = <...>;



The secondary-boot-reg property is a u32 value that specifies the

physical address of the register used to request the ROM holding pen

code release a secondary CPU.  The value written to the register is

formed by encoding the target CPU id into the low bits of the

physical start address it should jump to.



Example:

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <0>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a9";

			reg = <1>;

			enable-method = "brcm,bcm23550";

			secondary-boot-reg = <0x3500417c>;

		};

	};

Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt

0 → 100644
+15 −0
Original line number Diff line number Diff line 
Broadcom BCM23550 device tree bindings

--------------------------------------



This document describes the device tree bindings for boards with the BCM23550

SoC.



Required root node property:

  - compatible: brcm,bcm23550



Example:

	/ {

		model = "BCM23550 SoC";

		compatible = "brcm,bcm23550";

		[...]

	}

Documentation/devicetree/bindings/arm/cpus.txt

+2 −0
Original line number Diff line number Diff line
@@ -193,6 +193,8 @@ nodes to be present and contain the properties described below. 
			    "allwinner,sun6i-a31"

			    "allwinner,sun8i-a23"

			    "arm,realview-smp"

			    "brcm,bcm11351-cpu-method"

			    "brcm,bcm23550"

			    "brcm,bcm-nsp-smp"

			    "brcm,brahma-b15"

			    "marvell,armada-375-smp"

arch/arm/boot/dts/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -96,8 +96,11 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \ 
	bcm958305k.dtb

dtb-$(CONFIG_ARCH_BCM_MOBILE) += \

	bcm28155-ap.dtb \

	bcm21664-garnet.dtb

	bcm21664-garnet.dtb \

	bcm23550-sparrow.dtb

dtb-$(CONFIG_ARCH_BCM_NSP) += \

	bcm958525xmc.dtb \

	bcm958625hr.dtb \

	bcm958625k.dtb

dtb-$(CONFIG_ARCH_BERLIN) += \

	berlin2-sony-nsz-gs7.dtb \