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Commit be09d95e authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "arm64: Apply Erratum 1024718 to Kryo3xx Cores"

parents 304920be 9b3fa6bf

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -432,6 +432,20 @@ config ARM64_ERRATUM_843419 


	  If unsure, say Y.



config ARM64_ERRATUM_1024718

	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"

	default y

	help

	  This option adds work around for Arm Cortex-A55 Erratum 1024718.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect

	  update of the hardware dirty bit when the DBM/AP bits are updated

	  without a break-before-make. The work around is to disable the usage

	  of hardware DBM locally on the affected cores. CPUs not affected by

	  erratum will continue to use the feature.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/assembler.h

+40 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 


#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/cputype.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>

#include <asm/ptrace.h>
@@ -452,4 +453,43 @@ alternative_endif 
	mrs	\rd, sp_el0

	.endm



/*

 * Check the MIDR_EL1 of the current CPU for a given model and a range of

 * variant/revision. See asm/cputype.h for the macros used below.

 *

 *	model:		MIDR_CPU_MODEL of CPU

 *	rv_min:		Minimum of MIDR_CPU_VAR_REV()

 *	rv_max:		Maximum of MIDR_CPU_VAR_REV()

 *	res:		Result register.

 *	tmp1, tmp2, tmp3: Temporary registers

 *

 * Corrupts: res, tmp1, tmp2, tmp3

 * Returns:  0, if the CPU id doesn't match. Non-zero otherwise

 */

	.macro	cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3

	mrs		\res, midr_el1

	mov_q		\tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK)

	mov_q		\tmp2, MIDR_CPU_MODEL_MASK

	and		\tmp3, \res, \tmp2	// Extract model

	and		\tmp1, \res, \tmp1	// rev & variant

	mov_q		\tmp2, \model

	cmp		\tmp3, \tmp2

	cset		\res, eq

	cbz		\res, .Ldone\@		// Model matches ?



	.if (\rv_min != 0)			// Skip min check if rv_min == 0

	mov_q		\tmp3, \rv_min

	cmp		\tmp1, \tmp3

	cset		\res, ge

	.endif					// \rv_min != 0

	/* Skip rv_max check if rv_min == rv_max && rv_min != 0 */

	.if ((\rv_min != \rv_max) || \rv_min == 0)

	mov_q		\tmp2, \rv_max

	cmp		\tmp1, \tmp2

	cset		\tmp2, le

	and		\res, \res, \tmp2

	.endif

.Ldone\@:

	.endm



#endif	/* __ASM_ASSEMBLER_H */

arch/arm64/include/asm/cputype.h

+7 −0
Original line number Diff line number Diff line
@@ -56,6 +56,9 @@ 
	(0xf			<< MIDR_ARCHITECTURE_SHIFT) | \

	((partnum)		<< MIDR_PARTNUM_SHIFT))



#define MIDR_CPU_VAR_REV(var, rev) \

	(((var)	<< MIDR_VARIANT_SHIFT) | (rev))



#define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \

			     MIDR_ARCHITECTURE_MASK)
@@ -79,7 +82,9 @@ 
#define ARM_CPU_PART_CORTEX_A53		0xD03

#define ARM_CPU_PART_CORTEX_A73		0xD09

#define ARM_CPU_PART_CORTEX_A75		0xD0A

#define ARM_CPU_PART_KRYO3S		0x803

#define ARM_CPU_PART_KRYO3G		0x802

#define ARM_CPU_PART_CORTEX_A55		0xD05



#define APM_CPU_PART_POTENZA		0x000
@@ -93,7 +98,9 @@ 
#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)

#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)

#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)

#define MIDR_KRYO3S	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3S)

#define MIDR_KRYO3G	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO3G)

#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

arch/arm64/kernel/cpu_errata.c

+9 −6
Original line number Diff line number Diff line
@@ -180,8 +180,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
	/* Cortex-A57 r0p0 - r1p2 */

		.desc = "ARM erratum 832075",

		.capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,

		MIDR_RANGE(MIDR_CORTEX_A57, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 2),

		MIDR_RANGE(MIDR_CORTEX_A57,

			   MIDR_CPU_VAR_REV(0, 0),

			   MIDR_CPU_VAR_REV(1, 2)),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_834220
@@ -189,8 +190,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
	/* Cortex-A57 r0p0 - r1p2 */

		.desc = "ARM erratum 834220",

		.capability = ARM64_WORKAROUND_834220,

		MIDR_RANGE(MIDR_CORTEX_A57, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 2),

		MIDR_RANGE(MIDR_CORTEX_A57,

			   MIDR_CPU_VAR_REV(0, 0),

			   MIDR_CPU_VAR_REV(1, 2)),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_845719
@@ -214,8 +216,9 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
	/* Cavium ThunderX, T88 pass 1.x - 2.1 */

		.desc = "Cavium erratum 27456",

		.capability = ARM64_WORKAROUND_CAVIUM_27456,

		MIDR_RANGE(MIDR_THUNDERX, 0x00,

			   (1 << MIDR_VARIANT_SHIFT) | 1),

		MIDR_RANGE(MIDR_THUNDERX,

			   MIDR_CPU_VAR_REV(0, 0),

			   MIDR_CPU_VAR_REV(1, 1)),

	},

	{

	/* Cavium ThunderX, T81 pass 1.0 */