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Commit bdee4e26 authored by Steven King's avatar Steven King Committed by Greg Ungerer
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m68knommu: use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 



use MCF_IRQ_PIT1 instead of MCFINT_VECBASE + MCFINT_PIT1 so we can support
those parts that have the pit1 interrupt on other than the first interrupt
controller.

Signed-off-by: default avatarSteven King <sfking@fdwdc.com>
Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
parent bce4d12b

arch/m68k/include/asm/m520xsim.h

+1 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ 
#define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)



#define	MCF_IRQ_QSPI	    (MCFINT_VECBASE + MCFINT_QSPI)

#define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)



/*

 *  SDRAM configuration registers.

arch/m68k/include/asm/m523xsim.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)



#define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)

#define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)



/*

 *	SDRAM configuration registers.

arch/m68k/include/asm/m527xsim.h

+1 −0
Original line number Diff line number Diff line
@@ -60,6 +60,7 @@ 
#define	MCF_IRQ_FECENTC1	(MCFINT2_VECBASE + MCFINT2_FECENTC1)



#define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)

#define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)



/*

 *	SDRAM configuration registers.

arch/m68k/include/asm/m528xsim.h

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ 
#define	MCF_IRQ_FECENTC0	(MCFINT_VECBASE + MCFINT_FECENTC0)



#define	MCF_IRQ_QSPI		(MCFINT_VECBASE + MCFINT_QSPI)



#define MCF_IRQ_PIT1		(MCFINT_VECBASE + MCFINT_PIT1)

/*

 *	SDRAM configuration registers.

 */

arch/m68k/platform/coldfire/pit.c

+2 −2
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = { 
	.set_mode	= init_cf_pit_timer,

	.set_next_event	= cf_pit_next_event,

	.shift		= 32,

	.irq		= MCFINT_VECBASE + MCFINT_PIT1,

	.irq		= MCF_IRQ_PIT1,

};
@@ -159,7 +159,7 @@ void hw_timer_init(irq_handler_t handler) 
		clockevent_delta2ns(0x3f, &cf_pit_clockevent);

	clockevents_register_device(&cf_pit_clockevent);



	setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);

	setup_irq(MCF_IRQ_PIT1, &pit_irq);



	clocksource_register_hz(&pit_clk, FREQ);

}