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Commit bd833144 authored by Mario Kleiner's avatar Mario Kleiner Committed by Alex Deucher
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drm/amdgpu: Handle irqs only based on irq ring, not irq status regs. 



This is a translation of the patch ...
"drm/radeon: Handle irqs only based on irq ring, not irq status regs."
... for the vblank irq handling, to fix the same problem described
in that patch on the new driver.

Only compile tested due to lack of suitable hw.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarMario Kleiner <mario.kleiner.de@gmail.com>
CC: Michel Dänzer <michel.daenzer@amd.com>
CC: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 07f18f0b

drivers/gpu/drm/amd/amdgpu/dce_v10_0.c

+14 −8
Original line number Diff line number Diff line
@@ -3403,19 +3403,25 @@ static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 


	switch (entry->src_data) {

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v10_0_crtc_vblank_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			dce_v10_0_crtc_vline_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

drivers/gpu/drm/amd/amdgpu/dce_v11_0.c

+14 −8
Original line number Diff line number Diff line
@@ -3402,19 +3402,25 @@ static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 


	switch (entry->src_data) {

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			dce_v11_0_crtc_vblank_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			dce_v11_0_crtc_vline_int_ack(adev, crtc);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);

drivers/gpu/drm/amd/amdgpu/dce_v8_0.c

+14 −8
Original line number Diff line number Diff line
@@ -3237,19 +3237,25 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 


	switch (entry->src_data) {

	case 0: /* vblank */

		if (disp_int & interrupt_status_offsets[crtc].vblank) {

		if (disp_int & interrupt_status_offsets[crtc].vblank)

			WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		if (amdgpu_irq_enabled(adev, source, irq_type)) {

			drm_handle_vblank(adev->ddev, crtc);

		}

		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);

		}



		break;

	case 1: /* vline */

		if (disp_int & interrupt_status_offsets[crtc].vline) {

		if (disp_int & interrupt_status_offsets[crtc].vline)

			WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK);

		else

			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");



		DRM_DEBUG("IH: D%d vline\n", crtc + 1);

		}



		break;

	default:

		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);