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Commit bd4a68da authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-next 

More radeon and amdgpu changes for 4.9. Highlights:
- Initial SI support for amdgpu (controlled by a Kconfig option)
- misc ttm cleanups
- runtimepm fixes
- S3/S4 fixes
- power improvements
- lots of code cleanups and optimizations

* 'drm-next-4.9' of git://people.freedesktop.org/~agd5f/linux: (151 commits)
  drm/ttm: remove cpu_address member from ttm_tt
  drm/radeon/radeon_device: remove unused function
  drm/amdgpu: clean function declarations in amdgpu_ttm.c up
  drm/amdgpu: use the new ring ib and dma frame size callbacks (v2)
  drm/amdgpu/vce3: add ring callbacks for ib and dma frame size
  drm/amdgpu/vce2: add ring callbacks for ib and dma frame size
  drm/amdgpu/vce: add common ring callbacks for ib and dma frame size
  drm/amdgpu/uvd6: add ring callbacks for ib and dma frame size
  drm/amdgpu/uvd5: add ring callbacks for ib and dma frame size
  drm/amdgpu/uvd4.2: add ring callbacks for ib and dma frame size
  drm/amdgpu/sdma3: add ring callbacks for ib and dma frame size
  drm/amdgpu/sdma2.4: add ring callbacks for ib and dma frame size
  drm/amdgpu/cik_sdma: add ring callbacks for ib and dma frame size
  drm/amdgpu/si_dma: add ring callbacks for ib and dma frame size
  drm/amdgpu/gfx8: add ring callbacks for ib and dma frame size
  drm/amdgpu/gfx7: add ring callbacks for ib and dma frame size
  drm/amdgpu/gfx6: add ring callbacks for ib and dma frame size
  drm/amdgpu/ring: add an interface to get dma frame and ib size
  drm/amdgpu/sdma3: drop unused functions
  drm/amdgpu/gfx6: drop gds_switch callback
  ...
parents 9f8cf165 af1f85dd

drivers/gpu/drm/amd/amdgpu/Kconfig

+7 −0
Original line number Diff line number Diff line 
config DRM_AMDGPU_SI

	bool "Enable amdgpu support for SI parts"

	depends on DRM_AMDGPU

	help

	  Choose this option if you want to enable experimental support

	  for SI asics.



config DRM_AMDGPU_CIK

	bool "Enable amdgpu support for CIK parts"

	depends on DRM_AMDGPU

drivers/gpu/drm/amd/amdgpu/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ 
	ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \

	amdgpu_amdkfd_gfx_v7.o



amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o



amdgpu-y += \

	vi.o

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+52 −4
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ 
extern int amdgpu_modeset;

extern int amdgpu_vram_limit;

extern int amdgpu_gart_size;

extern int amdgpu_moverate;

extern int amdgpu_benchmarking;

extern int amdgpu_testing;

extern int amdgpu_audio;
@@ -94,6 +95,7 @@ extern unsigned amdgpu_pg_mask; 
extern char *amdgpu_disable_cu;

extern int amdgpu_sclk_deep_sleep_en;

extern char *amdgpu_virtual_display;

extern unsigned amdgpu_pp_feature_mask;



#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */
@@ -108,7 +110,7 @@ extern char *amdgpu_virtual_display; 
#define AMDGPU_MAX_RINGS			16

#define AMDGPU_MAX_GFX_RINGS			1

#define AMDGPU_MAX_COMPUTE_RINGS		8

#define AMDGPU_MAX_VCE_RINGS			2

#define AMDGPU_MAX_VCE_RINGS			3



/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		2
@@ -318,6 +320,10 @@ struct amdgpu_ring_funcs { 
	/* note usage for clock and power gating */

	void (*begin_use)(struct amdgpu_ring *ring);

	void (*end_use)(struct amdgpu_ring *ring);

	void (*emit_switch_buffer) (struct amdgpu_ring *ring);

	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);

	unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring);

	unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring);

};



/*
@@ -618,6 +624,7 @@ void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 
int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,

		     int pages, struct page **pagelist,

		     dma_addr_t *dma_addr, uint32_t flags);

int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);



/*

 * GPU MC structures, functions & helpers
@@ -963,6 +970,7 @@ struct amdgpu_ctx { 
	spinlock_t		ring_lock;

	struct fence            **fences;

	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];

	bool preamble_presented;

};



struct amdgpu_ctx_mgr {
@@ -1222,11 +1230,16 @@ struct amdgpu_cs_parser { 
	struct fence			*fence;

	uint64_t			bytes_moved_threshold;

	uint64_t			bytes_moved;

	struct amdgpu_bo_list_entry	*evictable;



	/* user fence */

	struct amdgpu_bo_list_entry	uf_entry;

};



#define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */

#define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */



struct amdgpu_job {

	struct amd_sched_job    base;

	struct amdgpu_device	*adev;
@@ -1235,9 +1248,10 @@ struct amdgpu_job { 
	struct amdgpu_sync	sync;

	struct amdgpu_ib	*ibs;

	struct fence		*fence; /* the hw fence */

	uint32_t		preamble_status;

	uint32_t		num_ibs;

	void			*owner;

	uint64_t		ctx;

	uint64_t		fence_ctx; /* the fence_context this job uses */

	bool                    vm_needs_flush;

	unsigned		vm_id;

	uint64_t		vm_pd_addr;
@@ -1686,6 +1700,7 @@ struct amdgpu_vce { 
	unsigned		harvest_config;

	struct amd_sched_entity	entity;

	uint32_t                srbm_soft_reset;

	unsigned		num_rings;

};



/*
@@ -1703,6 +1718,10 @@ struct amdgpu_sdma_instance { 


struct amdgpu_sdma {

	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];

#ifdef CONFIG_DRM_AMDGPU_SI

	//SI DMA has a difference trap irq number for the second engine

	struct amdgpu_irq_src	trap_irq_1;

#endif

	struct amdgpu_irq_src	trap_irq;

	struct amdgpu_irq_src	illegal_inst_irq;

	int			num_instances;
@@ -1819,6 +1838,9 @@ struct amdgpu_asic_funcs { 
	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);

	/* query virtual capabilities */

	u32 (*get_virtual_caps)(struct amdgpu_device *adev);

	/* static power management */

	int (*get_pcie_lanes)(struct amdgpu_device *adev);

	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);

};



/*
@@ -1993,6 +2015,8 @@ struct amdgpu_device { 
	spinlock_t pcie_idx_lock;

	amdgpu_rreg_t			pcie_rreg;

	amdgpu_wreg_t			pcie_wreg;

	amdgpu_rreg_t			pciep_rreg;

	amdgpu_wreg_t			pciep_wreg;

	/* protects concurrent UVD register access */

	spinlock_t uvd_ctx_idx_lock;

	amdgpu_rreg_t			uvd_ctx_rreg;
@@ -2033,6 +2057,14 @@ struct amdgpu_device { 
	atomic64_t			num_evictions;

	atomic_t			gpu_reset_counter;



	/* data for buffer migration throttling */

	struct {

		spinlock_t		lock;

		s64			last_update_us;

		s64			accum_us; /* accumulated microseconds */

		u32			log2_max_MBps;

	} mm_stats;



	/* display */

	bool				enable_virtual_display;

	struct amdgpu_mode_info		mode_info;
@@ -2101,6 +2133,10 @@ struct amdgpu_device { 
	/* link all shadow bo */

	struct list_head                shadow_list;

	struct mutex                    shadow_list_lock;

	/* link all gtt */

	spinlock_t			gtt_list_lock;

	struct list_head                gtt_list;



};



bool amdgpu_device_is_px(struct drm_device *dev);
@@ -2133,6 +2169,8 @@ void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 
#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))

#define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))

#define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))

#define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))

#define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))

#define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))

#define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
@@ -2223,6 +2261,9 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))

#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))

#define amdgpu_asic_get_virtual_caps(adev) ((adev)->asic_funcs->get_virtual_caps((adev)))

#define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))

#define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))

#define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
@@ -2244,9 +2285,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))

#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))

#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))

#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))

#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))

#define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))

#define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))

#define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))

#define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r))

#define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r))

#define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))

#define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))

#define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
@@ -2402,6 +2447,8 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);

u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);

int amdgpu_ttm_global_init(struct amdgpu_device *adev);

int amdgpu_ttm_init(struct amdgpu_device *adev);

void amdgpu_ttm_fini(struct amdgpu_device *adev);

void amdgpu_program_register_sequence(struct amdgpu_device *adev,

					     const u32 *registers,

					     const u32 array_size);
@@ -2434,8 +2481,8 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, 
				 struct drm_file *file_priv);

void amdgpu_driver_preclose_kms(struct drm_device *dev,

				struct drm_file *file_priv);

int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);

int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);

int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);

int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);

int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);

void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
@@ -2481,6 +2528,7 @@ static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 
struct amdgpu_bo_va_mapping *

amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,

		       uint64_t addr, struct amdgpu_bo **bo);

int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);



#include "amdgpu_object.h"

#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c

+158 −0
Original line number Diff line number Diff line
@@ -978,6 +978,48 @@ int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 
		return -EINVAL;



	switch (crev) {

	case 2:

	case 3:

	case 5:

		/* r6xx, r7xx, evergreen, ni, si.

		 * TODO: add support for asic_type <= CHIP_RV770*/

		if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {

			args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);



			amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);



			dividers->post_div = args.v3.ucPostDiv;

			dividers->enable_post_div = (args.v3.ucCntlFlag &

						     ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

			dividers->enable_dithen = (args.v3.ucCntlFlag &

						   ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

			dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);

			dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);

			dividers->ref_div = args.v3.ucRefDiv;

			dividers->vco_mode = (args.v3.ucCntlFlag &

					      ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;

		} else {

			/* for SI we use ComputeMemoryClockParam for memory plls */

			if (adev->asic_type >= CHIP_TAHITI)

				return -EINVAL;

			args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);

			if (strobe_mode)

				args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;



			amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);



			dividers->post_div = args.v5.ucPostDiv;

			dividers->enable_post_div = (args.v5.ucCntlFlag &

						     ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;

			dividers->enable_dithen = (args.v5.ucCntlFlag &

						   ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;

			dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);

			dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);

			dividers->ref_div = args.v5.ucRefDiv;

			dividers->vco_mode = (args.v5.ucCntlFlag &

					      ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;

		}

		break;

	case 4:

		/* fusion */

		args.v4.ulClock = cpu_to_le32(clock);	/* 10 khz */
@@ -1122,6 +1164,32 @@ void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 
	amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);

}



void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,

					  u16 *vddc, u16 *vddci, u16 *mvdd)

{

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);

	u8 frev, crev;

	u16 data_offset;

	union firmware_info *firmware_info;



	*vddc = 0;

	*vddci = 0;

	*mvdd = 0;



	if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,

				   &frev, &crev, &data_offset)) {

		firmware_info =

			(union firmware_info *)(mode_info->atom_context->bios +

						data_offset);

		*vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);

		if ((frev == 2) && (crev >= 2)) {

			*vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);

			*mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);

		}

	}

}



union set_voltage {

	struct _SET_VOLTAGE_PS_ALLOCATION alloc;

	struct _SET_VOLTAGE_PARAMETERS v1;
@@ -1129,6 +1197,52 @@ union set_voltage { 
	struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;

};



int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

			     u16 voltage_id, u16 *voltage)

{

	union set_voltage args;

	int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);

	u8 frev, crev;



	if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev))

		return -EINVAL;



	switch (crev) {

	case 1:

		return -EINVAL;

	case 2:

		args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;

		args.v2.ucVoltageMode = 0;

		args.v2.usVoltageLevel = 0;



		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);



		*voltage = le16_to_cpu(args.v2.usVoltageLevel);

		break;

	case 3:

		args.v3.ucVoltageType = voltage_type;

		args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;

		args.v3.usVoltageLevel = cpu_to_le16(voltage_id);



		amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);



		*voltage = le16_to_cpu(args.v3.usVoltageLevel);

		break;

	default:

		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);

		return -EINVAL;

	}



	return 0;

}



int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,

						      u16 *voltage,

						      u16 leakage_idx)

{

	return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);

}



void amdgpu_atombios_set_voltage(struct amdgpu_device *adev,

				 u16 voltage_level,

				 u8 voltage_type)
@@ -1349,6 +1463,50 @@ static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOL 
	return NULL;

}



int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,

			      u8 voltage_type,

			      u8 *svd_gpio_id, u8 *svc_gpio_id)

{

	int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);

	u8 frev, crev;

	u16 data_offset, size;

	union voltage_object_info *voltage_info;

	union voltage_object *voltage_object = NULL;



	if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size,

				   &frev, &crev, &data_offset)) {

		voltage_info = (union voltage_object_info *)

			(adev->mode_info.atom_context->bios + data_offset);



		switch (frev) {

		case 3:

			switch (crev) {

			case 1:

				voltage_object = (union voltage_object *)

					amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3,

								      voltage_type,

								      VOLTAGE_OBJ_SVID2);

				if (voltage_object) {

					*svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;

					*svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;

				} else {

					return -EINVAL;

				}

				break;

			default:

				DRM_ERROR("unknown voltage object table\n");

				return -EINVAL;

			}

			break;

		default:

			DRM_ERROR("unknown voltage object table\n");

			return -EINVAL;

		}



	}

	return 0;

}



bool

amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev,

				u8 voltage_type, u8 voltage_mode)

drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h

+15 −1
Original line number Diff line number Diff line
@@ -208,5 +208,19 @@ void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev); 
void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev);



void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);



int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type,

			     u16 voltage_id, u16 *voltage);

int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev,

						      u16 *voltage,

						      u16 leakage_idx);

void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev,

					  u16 *vddc, u16 *vddci, u16 *mvdd);

int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev,

				       u8 clock_type,

				       u32 clock,

				       bool strobe_mode,

				       struct atom_clock_dividers *dividers);

int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,

			      u8 voltage_type,

			      u8 *svd_gpio_id, u8 *svc_gpio_id);

#endif