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Commit bcd781f4 authored by Borislav Petkov's avatar Borislav Petkov
Browse files

amd64_edac: Cleanup NBSH cruft 



Remove reporting of errors with UC bit set - this is done by the MCE
decoding code anyway and this driver deals with DRAM ECC errors only. UC
(NB uncorrectable error) doesn't necessarily mean it is a DRAM error.
Remove unused macros while at it.

Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
parent a97fa68e

drivers/edac/amd64_edac.c

+2 −13
Original line number Diff line number Diff line
@@ -1748,7 +1748,7 @@ static void amd64_handle_ce(struct mem_ctl_info *mci, 
	u64 sys_addr;



	/* Ensure that the Error Address is VALID */

	if (!(info->nbsh & K8_NBSH_VALID_ERROR_ADDR)) {

	if (!(info->nbsh & NBSH_VALID_ERROR_ADDR)) {

		amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");

		edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);

		return;
@@ -1773,7 +1773,7 @@ static void amd64_handle_ue(struct mem_ctl_info *mci, 


	log_mci = mci;



	if (!(info->nbsh & K8_NBSH_VALID_ERROR_ADDR)) {

	if (!(info->nbsh & NBSH_VALID_ERROR_ADDR)) {

		amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");

		edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);

		return;
@@ -1839,17 +1839,6 @@ void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg) 
	regs.nbcfg = nbcfg;



	__amd64_decode_bus_error(mci, &regs);



	/*

	 * Check the UE bit of the NB status high register, if set generate some

	 * logs. If NOT a GART error, then process the event as a NO-INFO event.

	 * If it was a GART error, skip that process.

	 *

	 * FIXME: this should go somewhere else, if at all.

	 */

	if (regs.nbsh & K8_NBSH_UC_ERR && !report_gart_errors)

		edac_mc_handle_ue_no_info(mci, "UE bit is set");



}



/*

drivers/edac/mce_amd.c

+1 −1
Original line number Diff line number Diff line
@@ -604,7 +604,7 @@ void amd_decode_nb_mce(int node_id, struct mce *m, u32 nbcfg) 
	/* F10h, revD can disable ErrCpu[3:0] through ErrCpuVal */

	if ((boot_cpu_data.x86 == 0x10) &&

	    (boot_cpu_data.x86_model > 7)) {

		if (nbsh & K8_NBSH_ERR_CPU_VAL)

		if (nbsh & NBSH_ERR_CPU_VAL)

			core = nbsh & nb_err_cpumask;

	} else {

		u8 assoc_cpus = nbsh & nb_err_cpumask;

drivers/edac/mce_amd.h

+5 −13
Original line number Diff line number Diff line
@@ -31,19 +31,11 @@ 
#define R4(x)				(((x) >> 4) & 0xf)

#define R4_MSG(x)			((R4(x) < 9) ?  rrrr_msgs[R4(x)] : "Wrong R4!")



#define K8_NBSH				0x4C



#define K8_NBSH_VALID_BIT		BIT(31)

#define K8_NBSH_OVERFLOW		BIT(30)

#define K8_NBSH_UC_ERR			BIT(29)

#define K8_NBSH_ERR_EN			BIT(28)

#define K8_NBSH_MISCV			BIT(27)

#define K8_NBSH_VALID_ERROR_ADDR	BIT(26)

#define K8_NBSH_PCC			BIT(25)

#define K8_NBSH_ERR_CPU_VAL		BIT(24)

#define K8_NBSH_CECC			BIT(14)

#define K8_NBSH_UECC			BIT(13)

#define K8_NBSH_ERR_SCRUBER		BIT(8)

/*

 * F3x4C bits (MCi_STATUS' high half)

 */

#define NBSH_VALID_ERROR_ADDR		BIT(26)

#define NBSH_ERR_CPU_VAL		BIT(24)



enum tt_ids {

	TT_INSTR = 0,