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Commit bcc4d65a authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARCv2: MMUv4: support aliasing icache config 



This is also default for AXS103 release

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent d1f317d8

arch/arc/include/asm/cache.h

+1 −3
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ extern void read_decode_cache_bcr(void); 
#define ARC_REG_IC_IVIC		0x10

#define ARC_REG_IC_CTRL		0x11

#define ARC_REG_IC_IVIL		0x19

#if defined(CONFIG_ARC_MMU_V3)

#if defined(CONFIG_ARC_MMU_V3) || defined(CONFIG_ARC_MMU_V4)

#define ARC_REG_IC_PTAG		0x1E

#endif
@@ -74,9 +74,7 @@ extern void read_decode_cache_bcr(void); 
#define ARC_REG_DC_IVDL		0x4A

#define ARC_REG_DC_FLSH		0x4B

#define ARC_REG_DC_FLDL		0x4C

#if defined(CONFIG_ARC_MMU_V3)

#define ARC_REG_DC_PTAG		0x5C

#endif



/* Bit val in DC_CTRL */

#define DC_CTRL_INV_MODE_FLUSH  0x40

arch/arc/mm/cache.c

+13 −1
Original line number Diff line number Diff line
@@ -21,6 +21,9 @@ 
#include <asm/cachectl.h>

#include <asm/setup.h>



void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,

			       unsigned long sz, const int cacheop);



char *arc_cache_mumbojumbo(int c, char *buf, int len)

{

	int n = 0;
@@ -414,7 +417,7 @@ __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, 
	unsigned long flags;



	local_irq_save(flags);

	__cache_line_loop(paddr, vaddr, sz, OP_INV_IC);

	(*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);

	local_irq_restore(flags);

}
@@ -746,6 +749,15 @@ void arc_cache_init(void) 
		if (ic->ver != CONFIG_ARC_MMU_VER)

			panic("Cache ver [%d] doesn't match MMU ver [%d]\n",

			      ic->ver, CONFIG_ARC_MMU_VER);



		/*

		 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG

		 * pair to provide vaddr/paddr respectively, just as in MMU v3

		 */

		if (is_isa_arcv2() && ic->alias)

			_cache_line_loop_ic_fn = __cache_line_loop_v3;

		else

			_cache_line_loop_ic_fn = __cache_line_loop;

	}



	if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {