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Commit bc5e8fdf authored by Linus Torvalds's avatar Linus Torvalds
Browse files

x86-64/smp: fix random SIGSEGV issues 



They seem to have been due to AMD errata 63/122; the fix is to disable
TLB flush filtering in SMP configurations.

Confirmed to fix the problem by Andrew Walrond <andrew@walrond.org>

[ Let's see if we'll have a better fix eventually, this is the Q&D
  "let's get this fixed and out there" version ]

Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 61ffcafa

arch/x86_64/kernel/setup.c

+15 −0
Original line number Diff line number Diff line
@@ -831,11 +831,26 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c) 
#endif

}



#define HWCR 0xc0010015



static int __init init_amd(struct cpuinfo_x86 *c)

{

	int r;

	int level;



#ifdef CONFIG_SMP

	unsigned long value;



	// Disable TLB flush filter by setting HWCR.FFDIS:

	// bit 6 of msr C001_0015

	//

	// Errata 63 for SH-B3 steppings

	// Errata 122 for all(?) steppings

	rdmsrl(HWCR, value);

	value |= 1 << 6;

	wrmsrl(HWCR, value);

#endif



	/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;

	   3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */

	clear_bit(0*32+31, &c->x86_capability);