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Commit bc0ee9d2 authored by Jonathan Austin's avatar Jonathan Austin Committed by Russell King
Browse files

ARM: 8607/1: V7M: Wire up caches for V7M processors with cache support. 



This patch does the plumbing required to invoke the V7M cache code added
in earlier patches in this series, although there is no users for that
yet.

In order to honour the I/D cache disable config options, this patch changes
the mechanism by which the CCR is set on boot, to be more like V7A/R.

Signed-off-by: default avatarJonathan Austin <jonathan.austin@arm.com>
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Tested-by: default avatarAndras Szemzo <sza@esh.hu>
Tested-by: default avatarJoachim Eastwood <manabian@gmail.com>
Tested-by: default avatarAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 9a1af5f2

arch/arm/include/asm/glue-cache.h

+0 −4
Original line number Original line Diff line number Diff line
@@ -118,11 +118,7 @@ 
#endif

#endif





#if defined(CONFIG_CPU_V7M)

#if defined(CONFIG_CPU_V7M)

# ifdef _CACHE

#  define MULTI_CACHE 1

#  define MULTI_CACHE 1

# else

#  define _CACHE nop

# endif

#endif

#endif





#if !defined(_CACHE) && !defined(MULTI_CACHE)

#if !defined(_CACHE) && !defined(MULTI_CACHE)

arch/arm/kernel/head-nommu.S

+15 −1
Original line number Original line Diff line number Diff line
@@ -158,7 +158,21 @@ __after_proc_init: 
	bic	r0, r0, #CR_V

	bic	r0, r0, #CR_V

#endif

#endif

	mcr	p15, 0, r0, c1, c0, 0		@ write control reg

	mcr	p15, 0, r0, c1, c0, 0		@ write control reg

#endif /* CONFIG_CPU_CP15 */

#elif defined (CONFIG_CPU_V7M)

	/* For V7M systems we want to modify the CCR similarly to the SCTLR */

#ifdef CONFIG_CPU_DCACHE_DISABLE

	bic	r0, r0, #V7M_SCB_CCR_DC

#endif

#ifdef CONFIG_CPU_BPREDICT_DISABLE

	bic	r0, r0, #V7M_SCB_CCR_BP

#endif

#ifdef CONFIG_CPU_ICACHE_DISABLE

	bic	r0, r0, #V7M_SCB_CCR_IC

#endif

	movw	r3, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)

	movt	r3, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR)

	str	r0, [r3]

#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */

	ret	lr

	ret	lr

ENDPROC(__after_proc_init)

ENDPROC(__after_proc_init)

	.ltorg

	.ltorg

arch/arm/mm/Kconfig

+7 −3
Original line number Original line Diff line number Diff line
@@ -403,6 +403,7 @@ config CPU_V7M 
	bool

	bool

	select CPU_32v7M

	select CPU_32v7M

	select CPU_ABRT_NOMMU

	select CPU_ABRT_NOMMU

	select CPU_CACHE_V7M

	select CPU_CACHE_NOP

	select CPU_CACHE_NOP

	select CPU_PABRT_LEGACY

	select CPU_PABRT_LEGACY

	select CPU_THUMBONLY

	select CPU_THUMBONLY
@@ -518,6 +519,9 @@ config CPU_CACHE_VIPT 
config CPU_CACHE_FA

config CPU_CACHE_FA

	bool

	bool





config CPU_CACHE_V7M

	bool



if MMU

if MMU

# The copy-page model

# The copy-page model

config CPU_COPY_V4WT

config CPU_COPY_V4WT
@@ -750,14 +754,14 @@ config CPU_HIGH_VECTOR 




config CPU_ICACHE_DISABLE

config CPU_ICACHE_DISABLE

	bool "Disable I-Cache (I-bit)"

	bool "Disable I-Cache (I-bit)"

	depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)

	depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M

	help

	help

	  Say Y here to disable the processor instruction cache. Unless

	  Say Y here to disable the processor instruction cache. Unless

	  you have a reason not to or are unsure, say N.

	  you have a reason not to or are unsure, say N.





config CPU_DCACHE_DISABLE

config CPU_DCACHE_DISABLE

	bool "Disable D-Cache (C-bit)"

	bool "Disable D-Cache (C-bit)"

	depends on CPU_CP15 && !SMP

	depends on (CPU_CP15 && !SMP) || CPU_V7M

	help

	help

	  Say Y here to disable the processor data cache. Unless

	  Say Y here to disable the processor data cache. Unless

	  you have a reason not to or are unsure, say N.

	  you have a reason not to or are unsure, say N.
@@ -792,7 +796,7 @@ config CPU_CACHE_ROUND_ROBIN 




config CPU_BPREDICT_DISABLE

config CPU_BPREDICT_DISABLE

	bool "Disable branch prediction"

	bool "Disable branch prediction"

	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526

	depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M

	help

	help

	  Say Y here to disable branch prediction.  If unsure, say N.

	  Say Y here to disable branch prediction.  If unsure, say N.

arch/arm/mm/Makefile

+2 −0
Original line number Original line Diff line number Diff line
@@ -43,9 +43,11 @@ obj-$(CONFIG_CPU_CACHE_V6) += cache-v6.o 
obj-$(CONFIG_CPU_CACHE_V7)	+= cache-v7.o

obj-$(CONFIG_CPU_CACHE_V7)	+= cache-v7.o

obj-$(CONFIG_CPU_CACHE_FA)	+= cache-fa.o

obj-$(CONFIG_CPU_CACHE_FA)	+= cache-fa.o

obj-$(CONFIG_CPU_CACHE_NOP)	+= cache-nop.o

obj-$(CONFIG_CPU_CACHE_NOP)	+= cache-nop.o

obj-$(CONFIG_CPU_CACHE_V7M)	+= cache-v7m.o





AFLAGS_cache-v6.o	:=-Wa,-march=armv6

AFLAGS_cache-v6.o	:=-Wa,-march=armv6

AFLAGS_cache-v7.o	:=-Wa,-march=armv7-a

AFLAGS_cache-v7.o	:=-Wa,-march=armv7-a

AFLAGS_cache-v7m.o	:=-Wa,-march=armv7-m





obj-$(CONFIG_CPU_COPY_V4WT)	+= copypage-v4wt.o

obj-$(CONFIG_CPU_COPY_V4WT)	+= copypage-v4wt.o

obj-$(CONFIG_CPU_COPY_V4WB)	+= copypage-v4wb.o

obj-$(CONFIG_CPU_COPY_V4WB)	+= copypage-v4wb.o

arch/arm/mm/proc-v7m.S

+2 −3
Original line number Original line Diff line number Diff line
@@ -118,9 +118,8 @@ __v7m_setup: 




	@ Configure the System Control Register to ensure 8-byte stack alignment

	@ Configure the System Control Register to ensure 8-byte stack alignment

	@ Note the STKALIGN bit is either RW or RAO.

	@ Note the STKALIGN bit is either RW or RAO.

	ldr	r12, [r0, V7M_SCB_CCR]	@ system control register

	ldr	r0, [r0, V7M_SCB_CCR]   @ system control register

	orr	r12, #V7M_SCB_CCR_STKALIGN

	orr	r0, #V7M_SCB_CCR_STKALIGN

	str	r12, [r0, V7M_SCB_CCR]

	ret	lr

	ret	lr

ENDPROC(__v7m_setup)

ENDPROC(__v7m_setup)