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Commit bbf0a305 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: dmm32at: rename DMM32AT_CNTRDIO 



For aesthetics, rename this define used for the Counter and Digital I/O
Configuration register. Define the bits of the register.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 990c96d1

drivers/staging/comedi/drivers/dmm32at.c

+10 −7
Original line number Diff line number Diff line
@@ -91,8 +91,14 @@ Configuration Options: 
#define DMM32AT_INTCLK_TINT		(1 << 5)

#define DMM32AT_INTCLK_CLKEN		(1 << 1)  /* 1=see below  0=software */

#define DMM32AT_INTCLK_CLKSEL		(1 << 0)  /* 1=OUT2  0=EXTCLK */



#define DMM32AT_CNTRDIO 0x0a

#define DMM32AT_CTRDIO_CFG_REG		0x0a

#define DMM32AT_CTRDIO_CFG_FREQ12	(1 << 7)  /* CLK12 1=100KHz 0=10MHz */

#define DMM32AT_CTRDIO_CFG_FREQ0	(1 << 6)  /* CLK0  1=10KHz  0=10MHz */

#define DMM32AT_CTRDIO_CFG_OUT2EN	(1 << 5)  /* J3.42 1=OUT2 is DOUT2 */

#define DMM32AT_CTRDIO_CFG_OUT0EN	(1 << 4)  /* J3,44 1=OUT0 is DOUT0 */

#define DMM32AT_CTRDIO_CFG_GT0EN	(1 << 2)  /* J3.47 1=DIN1 is GATE0 */

#define DMM32AT_CTRDIO_CFG_SRC0		(1 << 1)  /* CLK0 is 0=FREQ0 1=J3.48 */

#define DMM32AT_CTRDIO_CFG_GT12EN	(1 << 0)  /* J3.46 1=DIN2 is GATE12 */



#define DMM32AT_AICONF 0x0b

#define DMM32AT_AIRBACK 0x0b
@@ -105,9 +111,6 @@ Configuration Options: 


/* Board register values. */



/* DMM32AT_CNTRDIO 0x0a */

#define DMM32AT_FREQ12 0x80



/* DMM32AT_AICONF 0x0b */

#define DMM32AT_RANGE_U10 0x0c

#define DMM32AT_RANGE_U5 0x0d
@@ -334,8 +337,8 @@ static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec) 
	hi2 = (both2 & 0xff00) >> 8;

	lo2 = both2 & 0x00ff;



	/* set the counter frequency to 10mhz */

	outb(0, dev->iobase + DMM32AT_CNTRDIO);

	/* set counter clocks to 10MHz, disable all aux dio */

	outb(0, dev->iobase + DMM32AT_CTRDIO_CFG_REG);



	/* get access to the clock regs */

	outb(DMM32AT_CTRL_PAGE_8254, dev->iobase + DMM32AT_CTRL_REG);