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Commit bbe30b3b authored Oct 15, 2013 by Anton Blanchard Committed by Benjamin Herrenschmidt Oct 30, 2013

powerpc: Use 32 bit loads and stores when operating on condition register values



The condition register (CR) is a 32 bit quantity so we should use
32 bit loads and stores.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

parent 65508689

arch/powerpc/kernel/tm.S

+4 −4

Original line number	Diff line number	Diff line
		@@ -106,7 +106,7 @@ DSCR_DEFAULT:
		_GLOBAL(tm_reclaim)
		mfcr r6
		mflr r0
		std r6, 8(r1)
		stw r6, 8(r1)
		std r0, 16(r1)
		std r2, 40(r1)
		stdu r1, -TM_FRAME_SIZE(r1)
		@@ -285,7 +285,7 @@ dont_backup_fp:
		REST_NVGPRS(r1)

		addi r1, r1, TM_FRAME_SIZE
		ld r4, 8(r1)
		lwz r4, 8(r1)
		ld r0, 16(r1)
		mtcr r4
		mtlr r0
		@@ -310,7 +310,7 @@ dont_backup_fp:
		_GLOBAL(tm_recheckpoint)
		mfcr r5
		mflr r0
		std r5, 8(r1)
		stw r5, 8(r1)
		std r0, 16(r1)
		std r2, 40(r1)
		stdu r1, -TM_FRAME_SIZE(r1)
		@@ -444,7 +444,7 @@ restore_gprs:
		REST_NVGPRS(r1)

		addi r1, r1, TM_FRAME_SIZE
		ld r4, 8(r1)
		lwz r4, 8(r1)
		ld r0, 16(r1)
		mtcr r4
		mtlr r0

arch/powerpc/platforms/powernv/opal-wrappers.S

+2 −2

Original line number	Diff line number	Diff line
		@@ -24,7 +24,7 @@
		mflr r0; \
		mfcr r12; \
		std r0,16(r1); \
		std r12,8(r1); \
		stw r12,8(r1); \
		std r1,PACAR1(r13); \
		li r0,0; \
		mfmsr r12; \
		@@ -53,7 +53,7 @@ _STATIC(opal_return)
		*/
		FIXUP_ENDIAN
		ld r2,PACATOC(r13);
		ld r4,8(r1);
		lwz r4,8(r1);
		ld r5,16(r1);
		ld r6,PACASAVEDMSR(r13);
		mtspr SPRN_SRR0,r5;