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Commit bbc2f005 authored by Satish Kumar Kurada's avatar Satish Kumar Kurada Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add Graphics support msm8909w GPU 



Add initial version of msm8909 GPU properties.

This is needed to support graphics driver functionality on msm8909 target.

Change-Id: I2629e0aff8d183869816ae89e3400c4b19faef1e
Signed-off-by: default avatarSundara Vinayagam <sundvi@codeaurora.org>
Signed-off-by: default avatarChinkit Kumar,Kirti Kumar Parmar <parma@codeaurora.org>
parent 6aa9a864

arch/arm64/boot/dts/qcom/msm8909-gpu.dtsi

0 → 100644
+149 −0
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



&soc {

	msm_bus: qcom,kgsl-busmon {

		label = "kgsl-busmon";

		compatible = "qcom,kgsl-busmon";

	};



	/* To use BIMC based bus governor */

	gpubw: qcom,gpubw {

		compatible = "qcom,devbw";

		governor = "bw_hwmon";

		qcom,src-dst-ports = <26 512>;

		qcom,bw-tbl =

			<    0 >,	/*   9.6 MHz */

			<  381 >,	/*  50.0 MHz */

			<  762 >,	/* 100.0 MHz */

			< 1525 >,	/* 200.0 MHz */

			< 3051 >,	/* 400.0 MHz */

			< 4066 >;	/* 533.0 MHz */

	};



	qcom,gpu-bwmon@410000 {

		compatible = "qcom,bimc-bwmon2";

		reg = <0x00410000 0x300>, <0x00401000 0x200>;

		reg-names = "base", "global_base";

		interrupts = <0 183 4>;

		qcom,mport = <2>;

		qcom,target-dev = <&gpubw>;

	};



	msm_gpu: qcom,kgsl-3d0@01c00000 {

		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x01c00000 0x10000

		       0x01c10000 0x10000

		       0x0005c000 0x204>;

		reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory" ,

			    "qfprom_memory";

		interrupts = <0 33 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;



		qcom,chipid = <0x03000400>;



		qcom,initial-pwrlevel = <1>;



		qcom,idle-timeout = <80>; /* msec */

		qcom,strtstp-sleepwake;

		qcom,gpu-disable-fuse = <0x44 0x00000001 27>;



		/*

		 * Clocks = KGSL_CLK_CORE | KGSL_CLK_IFACE |

		 * KGSL_CLK_MEM_IFACE | KGSL_CLK_ALT_MEM_IFACE

		 */

		qcom,clk-map = <0x00000056>;

		clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>,

			<&clock_gcc clk_gcc_oxili_ahb_clk>,

			<&clock_gcc clk_gcc_bimc_gfx_clk>,

			<&clock_gcc clk_gcc_bimc_gpu_clk>,

			<&clock_gcc clk_gcc_gtcu_ahb_clk>;

		clock-names = "core_clk", "iface_clk",

				"mem_iface_clk", "alt_mem_iface_clk",

				"gtcu_iface_clk";



		/* Bus Scale Settings */

		qcom,gpubw-dev = <&gpubw>;

		qcom,msm-bus,name = "grp3d";

		qcom,msm-bus,num-cases = <4>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<26 512 0 0>,

			<26 512 0 1600000>,

			<26 512 0 3200000>,

			<26 512 0 4264000>;



		/* GDSC oxili regulators */

		vdd-supply = <&gdsc_oxili_gx>;



		/* CPU latency parameter */

		qcom,pm-qos-active-latency = <701>;

		qcom,pm-qos-wakeup-latency = <701>;



		/* Power levels */

		qcom,gpu-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,gpu-pwrlevels";



			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <456000000>;

				qcom,bus-freq = <3>;

			};



			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <307200000>;

				qcom,bus-freq = <2>;

			};



			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <200000000>;

				qcom,bus-freq = <1>;

			};



			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

			};

		};



	};

	kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {

		compatible = "qcom,kgsl-smmu-v2";

		reg = <0x1f00000 0x10000>;

		/*

		 * The gpu can only program a single context bank

		 * at this fixed offset.

		 */

		qcom,protect = <0xa000 0x1000>;

		clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>,

				<&clock_gcc clk_gcc_gfx_tcu_clk>,

				<&clock_gcc clk_gcc_gtcu_ahb_clk>,

				<&clock_gcc clk_gcc_gfx_tbu_clk>;

				clock-names = "scfg_clk", "gtcu_clk",

				"gtcu_iface_clk", "gtbu_clk";

		qcom,retention;

		gfx3d_user: gfx3d_user {

			compatible = "qcom,smmu-kgsl-cb";

			iommus = <&kgsl_smmu 0>;

			qcom,gpu-offset = <0xa000>;

		};

	};

};

arch/arm64/boot/dts/qcom/msm8909.dtsi

+1 −0
Original line number Original line Diff line number Diff line
@@ -220,6 +220,7 @@ 
#include "msm8909-smp2p.dtsi"

#include "msm8909-smp2p.dtsi"

#include "msm8909-ipcrouter.dtsi"

#include "msm8909-ipcrouter.dtsi"

#include "msm-gdsc-8916.dtsi"

#include "msm-gdsc-8916.dtsi"

#include "msm8909-gpu.dtsi"

#include "msm8909-coresight.dtsi"

#include "msm8909-coresight.dtsi"

#include "msm8909-bus.dtsi"

#include "msm8909-bus.dtsi"

#include "msm8909-mdss.dtsi"

#include "msm8909-mdss.dtsi"

arch/arm64/boot/dts/qcom/msm8909w-bg-wtp-v2.dts

+1 −0
Original line number Original line Diff line number Diff line
@@ -14,6 +14,7 @@ 
/dts-v1/;

/dts-v1/;





#include "msm8909-mtp.dtsi"

#include "msm8909-mtp.dtsi"

#include "msm8909w-gpu.dtsi"

#include "msm8909w.dtsi"

#include "msm8909w.dtsi"

#include "msm8909w-bg-memory.dtsi"

#include "msm8909w-bg-memory.dtsi"

#include "8909w-pm660.dtsi"

#include "8909w-pm660.dtsi"

arch/arm64/boot/dts/qcom/msm8909w-gpu.dtsi

0 → 100644
+62 −0
Original line number Original line Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



/* To use BIMC based bus governor */

&gpubw {

	qcom,bw-tbl =

		<    0 >,	/*   9.6 MHz */

		<  366 >,	/*  48.0 MHz */

		<  732 >,	/*  96.0 MHz */

		< 1464 >,	/* 192.0 MHz */

		< 2929 >;	/* 384.0 MHz */

};



&msm_gpu {



	/* To disable GPU wake up on touch event */

	qcom,disable-wake-on-touch;



	/* Bus Scale Settings */

	qcom,msm-bus,num-cases = <3>;

	qcom,msm-bus,vectors-KBps =

		<26 512 0 0>,

		<26 512 0 1536000>,

		<26 512 0 3070000>;



	/delete-node/qcom,gpu-pwrlevels;



	/* Power levels */

	qcom,gpu-pwrlevels {

		#address-cells = <1>;

		#size-cells = <0>;



		compatible = "qcom,gpu-pwrlevels";



		qcom,gpu-pwrlevel@0 {

			reg = <0>;

			qcom,gpu-freq = <200000000>;

			qcom,bus-freq = <1>;

			qcom,bus-min = <1>;

			qcom,bus-max = <1>;

		};



		qcom,gpu-pwrlevel@1 {

			reg = <1>;

			qcom,gpu-freq = <19200000>;

			qcom,bus-freq = <0>;

			qcom,bus-min = <0>;

			qcom,bus-max = <0>;

		};



	};



};