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Commit bb0d977e authored by Stephane Eranian's avatar Stephane Eranian Committed by Andi Kleen
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[PATCH] i386: add Intel Core related PMU MSRs 



- add Intel Precise-Event Based sampling (PEBS) related MSR
- add Intel Data Save (DS) Area related MSR
- add Intel Core microarchitecure performance counter MSRs

Signed-off-by: default avatarstephane eranian <eranian@hpl.hp.com>
Signed-off-by: default avatarAndi Kleen <ak@suse.de>
parent 86efef50

include/asm-i386/msr.h

+13 −0
Original line number Diff line number Diff line
@@ -141,6 +141,10 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) 
#define MSR_IA32_MC0_ADDR		0x402

#define MSR_IA32_MC0_MISC		0x403



#define MSR_IA32_PEBS_ENABLE		0x3f1

#define MSR_IA32_DS_AREA		0x600

#define MSR_IA32_PERF_CAPABILITIES	0x345



/* Pentium IV performance counter MSRs */

#define MSR_P4_BPU_PERFCTR0 		0x300

#define MSR_P4_BPU_PERFCTR1 		0x301
@@ -284,4 +288,13 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val) 
#define MSR_TMTA_LRTI_READOUT		0x80868018

#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a



/* Intel Core-based CPU performance counters */

#define MSR_CORE_PERF_FIXED_CTR0	0x309

#define MSR_CORE_PERF_FIXED_CTR1	0x30a

#define MSR_CORE_PERF_FIXED_CTR2	0x30b

#define MSR_CORE_PERF_FIXED_CTR_CTRL	0x38d

#define MSR_CORE_PERF_GLOBAL_STATUS	0x38e

#define MSR_CORE_PERF_GLOBAL_CTRL	0x38f

#define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x390



#endif /* __ASM_MSR_H */