Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit bafb8192 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'xtensa-next-20140224' of git://github.com/czankel/xtensa-linux 

Pull tensa fixes from Chris Zankel:
 "This series includes fixes for potentially serious bugs in the
  routines spilling processor registers to stack, as well as other
  issues and compiler errors and warnings.

   - allow booting xtfpga on boards with new uBoot and >128MBytes memory
   - drop nonexistent GPIO32 support from fsf variant
   - don't select USE_GENERIC_SMP_HELPERS
   - enable common clock framework support, set up ethoc clock on xtfpga
   - wire up sched_setattr and sched_getattr syscalls.
   - fix system call to spill the processor registers to stack.
   - improve kernel macro to spill the processor registers
   - export ccount_freq symbol
   - fix undefined symbol warning"

* tag 'xtensa-next-20140224' of git://github.com/czankel/xtensa-linux:
  xtensa: wire up sched_setattr and sched_getattr syscalls
  xtensa: xtfpga: set ethoc clock frequency
  xtensa: xtfpga: use common clock framework
  xtensa: support common clock framework
  xtensa: no need to select USE_GENERIC_SMP_HELPERS
  xtensa: fsf: drop nonexistent GPIO32 support
  xtensa: don't pass high memory to bootmem allocator
  xtensa: fix fast_syscall_spill_registers
  xtensa: fix fast_syscall_spill_registers
  xtensa: save current register frame in fast_syscall_spill_registers_fixup
  xtensa: introduce spill_registers_kernel macro
  xtensa: export ccount_freq
  xtensa: fix warning '"CONFIG_OF" is not defined'
parents 7472e009 b3fdfc1b

arch/xtensa/Kconfig

+1 −2
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ config XTENSA 
	select HAVE_FUNCTION_TRACER

	select HAVE_IRQ_TIME_ACCOUNTING

	select HAVE_PERF_EVENTS

	select COMMON_CLK

	help

	  Xtensa processors are 32-bit RISC machines designed by Tensilica

	  primarily for embedded systems.  These processors are both
@@ -80,7 +81,6 @@ choice 
config XTENSA_VARIANT_FSF

	bool "fsf - default (not generic) configuration"

	select MMU

	select HAVE_XTENSA_GPIO32



config XTENSA_VARIANT_DC232B

	bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
@@ -135,7 +135,6 @@ config HAVE_SMP 
config SMP

	bool "Enable Symmetric multi-processing support"

	depends on HAVE_SMP

	select USE_GENERIC_SMP_HELPERS

	select GENERIC_SMP_IDLE_THREAD

	help

	  Enabled SMP Software; allows more than one CPU/CORE

arch/xtensa/boot/dts/xtfpga.dtsi

+9 −3
Original line number Diff line number Diff line
@@ -35,6 +35,13 @@ 
		interrupt-controller;

	};



	clocks {

		osc: main-oscillator {

			#clock-cells = <0>;

			compatible = "fixed-clock";

		};

	};



	serial0: serial@fd050020 {

		device_type = "serial";

		compatible = "ns16550a";
@@ -42,9 +49,7 @@ 
		reg = <0xfd050020 0x20>;

		reg-shift = <2>;

		interrupts = <0 1>; /* external irq 0 */

		/* Filled in by platform_setup from FPGA register

		 * clock-frequency = <100000000>;

		 */

		clocks = <&osc>;

	};



	enet0: ethoc@fd030000 {
@@ -52,5 +57,6 @@ 
		reg = <0xfd030000 0x4000 0xfd800000 0x4000>;

		interrupts = <1 1>; /* external irq 1 */

		local-mac-address = [00 50 c2 13 6f 00];

		clocks = <&osc>;

	};

};

arch/xtensa/include/asm/io.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 


#ifdef CONFIG_MMU



#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF

#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)

extern unsigned long xtensa_kio_paddr;



static inline unsigned long xtensa_get_kio_paddr(void)

arch/xtensa/include/asm/traps.h

+28 −16
Original line number Diff line number Diff line
@@ -23,25 +23,37 @@ void secondary_trap_init(void); 


static inline void spill_registers(void)

{



#if XCHAL_NUM_AREGS > 16

	__asm__ __volatile__ (

		"movi	a14, "__stringify((1 << PS_EXCM_BIT) | LOCKLEVEL)"\n\t"

		"mov	a12, a0\n\t"

		"rsr	a13, sar\n\t"

		"xsr	a14, ps\n\t"

		"movi	a0, _spill_registers\n\t"

		"rsync\n\t"

		"callx0 a0\n\t"

		"mov	a0, a12\n\t"

		"wsr	a13, sar\n\t"

		"wsr	a14, ps\n\t"

		: :

#if defined(CONFIG_FRAME_POINTER)

		: "a2", "a3", "a4",       "a11", "a12", "a13", "a14", "a15",

		"	call12	1f\n"

		"	_j	2f\n"

		"	retw\n"

		"	.align	4\n"

		"1:\n"

		"	_entry	a1, 48\n"

		"	addi	a12, a0, 3\n"

#if XCHAL_NUM_AREGS > 32

		"	.rept	(" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n"

		"	_entry	a1, 48\n"

		"	mov	a12, a0\n"

		"	.endr\n"

#endif

		"	_entry	a1, 48\n"

#if XCHAL_NUM_AREGS % 12 == 0

		"	mov	a8, a8\n"

#elif XCHAL_NUM_AREGS % 12 == 4

		"	mov	a12, a12\n"

#elif XCHAL_NUM_AREGS % 12 == 8

		"	mov	a4, a4\n"

#endif

		"	retw\n"

		"2:\n"

		: : : "a12", "a13", "memory");

#else

		: "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15",

	__asm__ __volatile__ (

		"	mov	a12, a12\n"

		: : : "memory");

#endif

		  "memory");

}



#endif /* _XTENSA_TRAPS_H */

arch/xtensa/include/asm/vectors.h

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
#define XCHAL_KIO_DEFAULT_PADDR		0xf0000000

#define XCHAL_KIO_SIZE			0x10000000



#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && CONFIG_OF

#if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY && defined(CONFIG_OF)

#define XCHAL_KIO_PADDR			xtensa_get_kio_paddr()

#else

#define XCHAL_KIO_PADDR			XCHAL_KIO_DEFAULT_PADDR