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Commit baa03522 authored by Tiejun Chen's avatar Tiejun Chen Committed by Paolo Bonzini
Browse files

kvm: x86: vmx: reorder some msr writing 



The commit 34a1cd60, "x86: vmx: move some vmx setting from
vmx_init() to hardware_setup()", tried to refactor some codes
specific to vmx hardware setting into hardware_setup(), but some
msr writing should depend on our previous setting condition like
enable_apicv, enable_ept and so on.

Reported-by: default avatarJamie Heilman <jamie@audible.transient.net>
Tested-by: default avatarJamie Heilman <jamie@audible.transient.net>
Signed-off-by: default avatarTiejun Chen <tiejun.chen@intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 97bf6af1

arch/x86/kvm/vmx.c

+44 −44
Original line number Diff line number Diff line
@@ -5840,49 +5840,6 @@ static __init int hardware_setup(void) 
	memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);

	memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);



	vmx_disable_intercept_for_msr(MSR_FS_BASE, false);

	vmx_disable_intercept_for_msr(MSR_GS_BASE, false);

	vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);

	vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);



	memcpy(vmx_msr_bitmap_legacy_x2apic,

			vmx_msr_bitmap_legacy, PAGE_SIZE);

	memcpy(vmx_msr_bitmap_longmode_x2apic,

			vmx_msr_bitmap_longmode, PAGE_SIZE);



	if (enable_apicv) {

		for (msr = 0x800; msr <= 0x8ff; msr++)

			vmx_disable_intercept_msr_read_x2apic(msr);



		/* According SDM, in x2apic mode, the whole id reg is used.

		 * But in KVM, it only use the highest eight bits. Need to

		 * intercept it */

		vmx_enable_intercept_msr_read_x2apic(0x802);

		/* TMCCT */

		vmx_enable_intercept_msr_read_x2apic(0x839);

		/* TPR */

		vmx_disable_intercept_msr_write_x2apic(0x808);

		/* EOI */

		vmx_disable_intercept_msr_write_x2apic(0x80b);

		/* SELF-IPI */

		vmx_disable_intercept_msr_write_x2apic(0x83f);

	}



	if (enable_ept) {

		kvm_mmu_set_mask_ptes(0ull,

			(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,

			(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,

			0ull, VMX_EPT_EXECUTABLE_MASK);

		ept_set_mmio_spte_mask();

		kvm_enable_tdp();

	} else

		kvm_disable_tdp();



	update_ple_window_actual_max();



	if (setup_vmcs_config(&vmcs_config) < 0) {

		r = -EIO;

		goto out7;
@@ -5945,6 +5902,49 @@ static __init int hardware_setup(void) 
	if (nested)

		nested_vmx_setup_ctls_msrs();



	vmx_disable_intercept_for_msr(MSR_FS_BASE, false);

	vmx_disable_intercept_for_msr(MSR_GS_BASE, false);

	vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);

	vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);

	vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);



	memcpy(vmx_msr_bitmap_legacy_x2apic,

			vmx_msr_bitmap_legacy, PAGE_SIZE);

	memcpy(vmx_msr_bitmap_longmode_x2apic,

			vmx_msr_bitmap_longmode, PAGE_SIZE);



	if (enable_apicv) {

		for (msr = 0x800; msr <= 0x8ff; msr++)

			vmx_disable_intercept_msr_read_x2apic(msr);



		/* According SDM, in x2apic mode, the whole id reg is used.

		 * But in KVM, it only use the highest eight bits. Need to

		 * intercept it */

		vmx_enable_intercept_msr_read_x2apic(0x802);

		/* TMCCT */

		vmx_enable_intercept_msr_read_x2apic(0x839);

		/* TPR */

		vmx_disable_intercept_msr_write_x2apic(0x808);

		/* EOI */

		vmx_disable_intercept_msr_write_x2apic(0x80b);

		/* SELF-IPI */

		vmx_disable_intercept_msr_write_x2apic(0x83f);

	}



	if (enable_ept) {

		kvm_mmu_set_mask_ptes(0ull,

			(enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,

			(enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,

			0ull, VMX_EPT_EXECUTABLE_MASK);

		ept_set_mmio_spte_mask();

		kvm_enable_tdp();

	} else

		kvm_disable_tdp();



	update_ple_window_actual_max();



	return alloc_kvm_area();



out7: