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Commit b997a8ba authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon: add register headers for CP DMA on r6xx-SI 



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6253e4c7

drivers/gpu/drm/radeon/evergreend.h

+47 −0
Original line number Diff line number Diff line
@@ -1035,6 +1035,53 @@ 
#define	PACKET3_WAIT_REG_MEM				0x3C

#define	PACKET3_MEM_WRITE				0x3D

#define	PACKET3_INDIRECT_BUFFER				0x32

#define	PACKET3_CP_DMA					0x41

/* 1. header

 * 2. SRC_ADDR_LO or DATA [31:0]

 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |

 *    SRC_ADDR_HI [7:0]

 * 4. DST_ADDR_LO [31:0]

 * 5. DST_ADDR_HI [7:0]

 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]

 */

#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 */

#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)

                /* 0 - ME

		 * 1 - PFP

		 */

#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 * 2 - DATA

		 */

#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)

/* COMMAND */

#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)

#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)

#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#define	PACKET3_SURFACE_SYNC				0x43

#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)

#              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)

drivers/gpu/drm/radeon/r600d.h

+32 −0
Original line number Diff line number Diff line
@@ -1186,6 +1186,38 @@ 
#define	PACKET3_WAIT_REG_MEM				0x3C

#define	PACKET3_MEM_WRITE				0x3D

#define	PACKET3_INDIRECT_BUFFER				0x32

#define	PACKET3_CP_DMA					0x41

/* 1. header

 * 2. SRC_ADDR_LO [31:0]

 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0]

 * 4. DST_ADDR_LO [31:0]

 * 5. DST_ADDR_HI [7:0]

 * 6. COMMAND [29:22] | BYTE_COUNT [20:0]

 */

#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)

/* COMMAND */

#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)

#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#define	PACKET3_SURFACE_SYNC				0x43

#              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)

#              define PACKET3_TC_ACTION_ENA        (1 << 23)

drivers/gpu/drm/radeon/sid.h

+48 −0
Original line number Diff line number Diff line
@@ -849,6 +849,54 @@ 
#define	PACKET3_WAIT_REG_MEM				0x3C

#define	PACKET3_MEM_WRITE				0x3D

#define	PACKET3_COPY_DATA				0x40

#define	PACKET3_CP_DMA					0x41

/* 1. header

 * 2. SRC_ADDR_LO or DATA [31:0]

 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |

 *    SRC_ADDR_HI [7:0]

 * 4. DST_ADDR_LO [31:0]

 * 5. DST_ADDR_HI [7:0]

 * 6. COMMAND [30:21] | BYTE_COUNT [20:0]

 */

#              define PACKET3_CP_DMA_DST_SEL(x)    ((x) << 20)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 */

#              define PACKET3_CP_DMA_ENGINE(x)     ((x) << 27)

                /* 0 - ME

		 * 1 - PFP

		 */

#              define PACKET3_CP_DMA_SRC_SEL(x)    ((x) << 29)

                /* 0 - SRC_ADDR

		 * 1 - GDS

		 * 2 - DATA

		 */

#              define PACKET3_CP_DMA_CP_SYNC       (1 << 31)

/* COMMAND */

#              define PACKET3_CP_DMA_DIS_WC        (1 << 21)

#              define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)

                /* 0 - none

		 * 1 - 8 in 16

		 * 2 - 8 in 32

		 * 3 - 8 in 64

		 */

#              define PACKET3_CP_DMA_CMD_SAS       (1 << 26)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_DAS       (1 << 27)

                /* 0 - memory

		 * 1 - register

		 */

#              define PACKET3_CP_DMA_CMD_SAIC      (1 << 28)

#              define PACKET3_CP_DMA_CMD_DAIC      (1 << 29)

#              define PACKET3_CP_DMA_CMD_RAW_WAIT  (1 << 30)

#define	PACKET3_PFP_SYNC_ME				0x42

#define	PACKET3_SURFACE_SYNC				0x43

#              define PACKET3_DEST_BASE_0_ENA      (1 << 0)