Loading arch/arm/configs/sa415m-perf_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,7 @@ CONFIG_PPP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CNSS2=y CONFIG_CNSS2=m CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CLD_HL_SDIO_CORE=y Loading arch/arm/configs/sa415m_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -225,7 +225,7 @@ CONFIG_PPP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CNSS2=y CONFIG_CNSS2=m CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CLD_HL_SDIO_CORE=y Loading drivers/net/wireless/cnss2/pci.c +2 −2 Original line number Diff line number Diff line Loading @@ -2155,8 +2155,8 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv) mhi_ctrl->iova_stop = pci_priv->smmu_iova_start + pci_priv->smmu_iova_len; } else { mhi_ctrl->iova_start = memblock_start_of_DRAM(); mhi_ctrl->iova_stop = memblock_end_of_DRAM(); mhi_ctrl->iova_start = 0; mhi_ctrl->iova_stop = (dma_addr_t)U64_MAX; } mhi_ctrl->link_status = cnss_mhi_link_status; Loading Loading
arch/arm/configs/sa415m-perf_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -224,7 +224,7 @@ CONFIG_PPP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CNSS2=y CONFIG_CNSS2=m CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CLD_HL_SDIO_CORE=y Loading
arch/arm/configs/sa415m_defconfig +1 −1 Original line number Diff line number Diff line Loading @@ -225,7 +225,7 @@ CONFIG_PPP=y CONFIG_PPPOL2TP=y CONFIG_PPP_ASYNC=y CONFIG_WCNSS_MEM_PRE_ALLOC=y CONFIG_CNSS2=y CONFIG_CNSS2=m CONFIG_CNSS2_DEBUG=y CONFIG_CNSS2_QMI=y CONFIG_CLD_HL_SDIO_CORE=y Loading
drivers/net/wireless/cnss2/pci.c +2 −2 Original line number Diff line number Diff line Loading @@ -2155,8 +2155,8 @@ static int cnss_pci_register_mhi(struct cnss_pci_data *pci_priv) mhi_ctrl->iova_stop = pci_priv->smmu_iova_start + pci_priv->smmu_iova_len; } else { mhi_ctrl->iova_start = memblock_start_of_DRAM(); mhi_ctrl->iova_stop = memblock_end_of_DRAM(); mhi_ctrl->iova_start = 0; mhi_ctrl->iova_stop = (dma_addr_t)U64_MAX; } mhi_ctrl->link_status = cnss_mhi_link_status; Loading