Loading drivers/gpu/msm/adreno.c +42 −0 Original line number Diff line number Diff line Loading @@ -1014,6 +1014,46 @@ static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev, return -ENODEV; } static void l3_pwrlevel_probe(struct kgsl_device *device, struct device_node *node) { struct device_node *pwrlevel_node, *child; pwrlevel_node = of_find_node_by_name(node, "qcom,l3-pwrlevels"); if (pwrlevel_node == NULL) return; device->num_l3_pwrlevels = 0; for_each_child_of_node(pwrlevel_node, child) { unsigned int index; if (of_property_read_u32(child, "reg", &index)) return; if (index >= MAX_L3_LEVELS) { dev_err(&device->pdev->dev, "L3 pwrlevel %d is out of range\n", index); continue; } if (index >= device->num_l3_pwrlevels) device->num_l3_pwrlevels = index + 1; if (of_property_read_u32(child, "qcom,l3-freq", &device->l3_freq[index])) return; } device->l3_clk = devm_clk_get(&device->pdev->dev, "l3_vote"); if (IS_ERR_OR_NULL(device->l3_clk)) { dev_err(&device->pdev->dev, "Unable to get the l3_vote clock\n"); return; } } static inline struct adreno_device *adreno_get_dev(struct platform_device *pdev) { const struct of_device_id *of_id = Loading Loading @@ -1060,6 +1100,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, /* Get context aware DCVS properties */ adreno_of_get_ca_aware_properties(adreno_dev, node); l3_pwrlevel_probe(device, node); /* get pm-qos-active-latency, set it to default if not found */ if (of_property_read_u32(node, "qcom,pm-qos-active-latency", &device->pwrctrl.pm_qos_active_latency)) Loading drivers/gpu/msm/adreno_ringbuffer.c +3 −52 Original line number Diff line number Diff line Loading @@ -762,54 +762,13 @@ adreno_ringbuffer_issue_internal_cmds(struct adreno_ringbuffer *rb, sizedwords, 0, NULL); } static int l3_pwrlevel_probe(struct kgsl_device *device, struct device_node *node) { struct device_node *pwrlevel_node, *child; pwrlevel_node = of_find_node_by_name(node, "qcom,l3-pwrlevels"); if (pwrlevel_node == NULL) { dev_err_once(&device->pdev->dev, "Unable to find 'qcom,l3-pwrlevels'\n"); return -EINVAL; } device->num_l3_pwrlevels = 0; for_each_child_of_node(pwrlevel_node, child) { unsigned int index; if (of_property_read_u32(child, "reg", &index)) return -EINVAL; if (index >= MAX_L3_LEVELS) { dev_err(&device->pdev->dev, "L3 pwrlevel %d is out of range\n", index); continue; } if (index >= device->num_l3_pwrlevels) device->num_l3_pwrlevels = index + 1; if (of_property_read_u32(child, "qcom,l3-freq", &device->l3_freq[index])) return -EINVAL; } return 0; } static void adreno_ringbuffer_set_constraint(struct kgsl_device *device, struct kgsl_drawobj *drawobj) { struct kgsl_context *context = drawobj->context; struct device *dev = &device->pdev->dev; unsigned long flags = drawobj->flags; struct device_node *node; node = device->pdev->dev.of_node; /* * Check if the context has a constraint and constraint flags are Loading @@ -821,22 +780,14 @@ static void adreno_ringbuffer_set_constraint(struct kgsl_device *device, kgsl_pwrctrl_set_constraint(device, &context->pwr_constraint, context->id); if (IS_ERR_OR_NULL(device->l3_clk)) device->l3_clk = devm_clk_get(dev, "l3_vote"); if (IS_ERR_OR_NULL(device->l3_clk)) { KGSL_DEV_ERR_ONCE(device, "Unable to get the l3_vote clock. Cannot set the L3 constraint\n"); return; } if (context->l3_pwr_constraint.type && ((context->flags & KGSL_CONTEXT_PWR_CONSTRAINT) || (flags & KGSL_CONTEXT_PWR_CONSTRAINT))) { int ret = l3_pwrlevel_probe(device, node); if (ret) if (IS_ERR_OR_NULL(device->l3_clk)) { KGSL_DEV_ERR_ONCE(device, "Cannot set L3 constraint\n"); return; } switch (context->l3_pwr_constraint.type) { Loading Loading
drivers/gpu/msm/adreno.c +42 −0 Original line number Diff line number Diff line Loading @@ -1014,6 +1014,46 @@ static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev, return -ENODEV; } static void l3_pwrlevel_probe(struct kgsl_device *device, struct device_node *node) { struct device_node *pwrlevel_node, *child; pwrlevel_node = of_find_node_by_name(node, "qcom,l3-pwrlevels"); if (pwrlevel_node == NULL) return; device->num_l3_pwrlevels = 0; for_each_child_of_node(pwrlevel_node, child) { unsigned int index; if (of_property_read_u32(child, "reg", &index)) return; if (index >= MAX_L3_LEVELS) { dev_err(&device->pdev->dev, "L3 pwrlevel %d is out of range\n", index); continue; } if (index >= device->num_l3_pwrlevels) device->num_l3_pwrlevels = index + 1; if (of_property_read_u32(child, "qcom,l3-freq", &device->l3_freq[index])) return; } device->l3_clk = devm_clk_get(&device->pdev->dev, "l3_vote"); if (IS_ERR_OR_NULL(device->l3_clk)) { dev_err(&device->pdev->dev, "Unable to get the l3_vote clock\n"); return; } } static inline struct adreno_device *adreno_get_dev(struct platform_device *pdev) { const struct of_device_id *of_id = Loading Loading @@ -1060,6 +1100,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, /* Get context aware DCVS properties */ adreno_of_get_ca_aware_properties(adreno_dev, node); l3_pwrlevel_probe(device, node); /* get pm-qos-active-latency, set it to default if not found */ if (of_property_read_u32(node, "qcom,pm-qos-active-latency", &device->pwrctrl.pm_qos_active_latency)) Loading
drivers/gpu/msm/adreno_ringbuffer.c +3 −52 Original line number Diff line number Diff line Loading @@ -762,54 +762,13 @@ adreno_ringbuffer_issue_internal_cmds(struct adreno_ringbuffer *rb, sizedwords, 0, NULL); } static int l3_pwrlevel_probe(struct kgsl_device *device, struct device_node *node) { struct device_node *pwrlevel_node, *child; pwrlevel_node = of_find_node_by_name(node, "qcom,l3-pwrlevels"); if (pwrlevel_node == NULL) { dev_err_once(&device->pdev->dev, "Unable to find 'qcom,l3-pwrlevels'\n"); return -EINVAL; } device->num_l3_pwrlevels = 0; for_each_child_of_node(pwrlevel_node, child) { unsigned int index; if (of_property_read_u32(child, "reg", &index)) return -EINVAL; if (index >= MAX_L3_LEVELS) { dev_err(&device->pdev->dev, "L3 pwrlevel %d is out of range\n", index); continue; } if (index >= device->num_l3_pwrlevels) device->num_l3_pwrlevels = index + 1; if (of_property_read_u32(child, "qcom,l3-freq", &device->l3_freq[index])) return -EINVAL; } return 0; } static void adreno_ringbuffer_set_constraint(struct kgsl_device *device, struct kgsl_drawobj *drawobj) { struct kgsl_context *context = drawobj->context; struct device *dev = &device->pdev->dev; unsigned long flags = drawobj->flags; struct device_node *node; node = device->pdev->dev.of_node; /* * Check if the context has a constraint and constraint flags are Loading @@ -821,22 +780,14 @@ static void adreno_ringbuffer_set_constraint(struct kgsl_device *device, kgsl_pwrctrl_set_constraint(device, &context->pwr_constraint, context->id); if (IS_ERR_OR_NULL(device->l3_clk)) device->l3_clk = devm_clk_get(dev, "l3_vote"); if (IS_ERR_OR_NULL(device->l3_clk)) { KGSL_DEV_ERR_ONCE(device, "Unable to get the l3_vote clock. Cannot set the L3 constraint\n"); return; } if (context->l3_pwr_constraint.type && ((context->flags & KGSL_CONTEXT_PWR_CONSTRAINT) || (flags & KGSL_CONTEXT_PWR_CONSTRAINT))) { int ret = l3_pwrlevel_probe(device, node); if (ret) if (IS_ERR_OR_NULL(device->l3_clk)) { KGSL_DEV_ERR_ONCE(device, "Cannot set L3 constraint\n"); return; } switch (context->l3_pwr_constraint.type) { Loading