Loading Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 37 SUBLEVEL = 38 EXTRAVERSION = NAME = Roaring Lionus Loading arch/x86/include/asm/pat.h +1 −0 Original line number Diff line number Diff line Loading @@ -7,6 +7,7 @@ bool pat_enabled(void); void pat_disable(const char *reason); extern void pat_init(void); extern void init_cache_modes(void); extern int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm); Loading arch/x86/kernel/setup.c +7 −0 Original line number Diff line number Diff line Loading @@ -1053,6 +1053,13 @@ void __init setup_arch(char **cmdline_p) max_possible_pfn = max_pfn; /* * This call is required when the CPU does not support PAT. If * mtrr_bp_init() invoked it already via pat_init() the call has no * effect. */ init_cache_modes(); /* * Define random base addresses for memory sections after max_pfn is * defined and before each memory section base is used. Loading arch/x86/mm/pat.c +12 −16 Original line number Diff line number Diff line Loading @@ -36,14 +36,14 @@ #undef pr_fmt #define pr_fmt(fmt) "" fmt static bool boot_cpu_done; static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT); static void init_cache_modes(void); static bool __read_mostly boot_cpu_done; static bool __read_mostly pat_disabled = !IS_ENABLED(CONFIG_X86_PAT); static bool __read_mostly pat_initialized; static bool __read_mostly init_cm_done; void pat_disable(const char *reason) { if (!__pat_enabled) if (pat_disabled) return; if (boot_cpu_done) { Loading @@ -51,10 +51,8 @@ void pat_disable(const char *reason) return; } __pat_enabled = 0; pat_disabled = true; pr_info("x86/PAT: %s\n", reason); init_cache_modes(); } static int __init nopat(char *str) Loading @@ -66,7 +64,7 @@ early_param("nopat", nopat); bool pat_enabled(void) { return !!__pat_enabled; return pat_initialized; } EXPORT_SYMBOL_GPL(pat_enabled); Loading Loading @@ -204,6 +202,8 @@ static void __init_cache_modes(u64 pat) update_cache_mode_entry(i, cache); } pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg); init_cm_done = true; } #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8)) Loading @@ -224,6 +224,7 @@ static void pat_bsp_init(u64 pat) } wrmsrl(MSR_IA32_CR_PAT, pat); pat_initialized = true; __init_cache_modes(pat); } Loading @@ -241,10 +242,9 @@ static void pat_ap_init(u64 pat) wrmsrl(MSR_IA32_CR_PAT, pat); } static void init_cache_modes(void) void init_cache_modes(void) { u64 pat = 0; static int init_cm_done; if (init_cm_done) return; Loading Loading @@ -286,8 +286,6 @@ static void init_cache_modes(void) } __init_cache_modes(pat); init_cm_done = 1; } /** Loading @@ -305,10 +303,8 @@ void pat_init(void) u64 pat; struct cpuinfo_x86 *c = &boot_cpu_data; if (!pat_enabled()) { init_cache_modes(); if (pat_disabled) return; } if ((c->x86_vendor == X86_VENDOR_INTEL) && (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || Loading crypto/rsa-pkcs1pad.c +1 −1 Original line number Diff line number Diff line Loading @@ -496,7 +496,7 @@ static int pkcs1pad_verify_complete(struct akcipher_request *req, int err) goto done; pos++; if (memcmp(out_buf + pos, digest_info->data, digest_info->size)) if (crypto_memneq(out_buf + pos, digest_info->data, digest_info->size)) goto done; pos += digest_info->size; Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line VERSION = 4 PATCHLEVEL = 9 SUBLEVEL = 37 SUBLEVEL = 38 EXTRAVERSION = NAME = Roaring Lionus Loading
arch/x86/include/asm/pat.h +1 −0 Original line number Diff line number Diff line Loading @@ -7,6 +7,7 @@ bool pat_enabled(void); void pat_disable(const char *reason); extern void pat_init(void); extern void init_cache_modes(void); extern int reserve_memtype(u64 start, u64 end, enum page_cache_mode req_pcm, enum page_cache_mode *ret_pcm); Loading
arch/x86/kernel/setup.c +7 −0 Original line number Diff line number Diff line Loading @@ -1053,6 +1053,13 @@ void __init setup_arch(char **cmdline_p) max_possible_pfn = max_pfn; /* * This call is required when the CPU does not support PAT. If * mtrr_bp_init() invoked it already via pat_init() the call has no * effect. */ init_cache_modes(); /* * Define random base addresses for memory sections after max_pfn is * defined and before each memory section base is used. Loading
arch/x86/mm/pat.c +12 −16 Original line number Diff line number Diff line Loading @@ -36,14 +36,14 @@ #undef pr_fmt #define pr_fmt(fmt) "" fmt static bool boot_cpu_done; static int __read_mostly __pat_enabled = IS_ENABLED(CONFIG_X86_PAT); static void init_cache_modes(void); static bool __read_mostly boot_cpu_done; static bool __read_mostly pat_disabled = !IS_ENABLED(CONFIG_X86_PAT); static bool __read_mostly pat_initialized; static bool __read_mostly init_cm_done; void pat_disable(const char *reason) { if (!__pat_enabled) if (pat_disabled) return; if (boot_cpu_done) { Loading @@ -51,10 +51,8 @@ void pat_disable(const char *reason) return; } __pat_enabled = 0; pat_disabled = true; pr_info("x86/PAT: %s\n", reason); init_cache_modes(); } static int __init nopat(char *str) Loading @@ -66,7 +64,7 @@ early_param("nopat", nopat); bool pat_enabled(void) { return !!__pat_enabled; return pat_initialized; } EXPORT_SYMBOL_GPL(pat_enabled); Loading Loading @@ -204,6 +202,8 @@ static void __init_cache_modes(u64 pat) update_cache_mode_entry(i, cache); } pr_info("x86/PAT: Configuration [0-7]: %s\n", pat_msg); init_cm_done = true; } #define PAT(x, y) ((u64)PAT_ ## y << ((x)*8)) Loading @@ -224,6 +224,7 @@ static void pat_bsp_init(u64 pat) } wrmsrl(MSR_IA32_CR_PAT, pat); pat_initialized = true; __init_cache_modes(pat); } Loading @@ -241,10 +242,9 @@ static void pat_ap_init(u64 pat) wrmsrl(MSR_IA32_CR_PAT, pat); } static void init_cache_modes(void) void init_cache_modes(void) { u64 pat = 0; static int init_cm_done; if (init_cm_done) return; Loading Loading @@ -286,8 +286,6 @@ static void init_cache_modes(void) } __init_cache_modes(pat); init_cm_done = 1; } /** Loading @@ -305,10 +303,8 @@ void pat_init(void) u64 pat; struct cpuinfo_x86 *c = &boot_cpu_data; if (!pat_enabled()) { init_cache_modes(); if (pat_disabled) return; } if ((c->x86_vendor == X86_VENDOR_INTEL) && (((c->x86 == 0x6) && (c->x86_model <= 0xd)) || Loading
crypto/rsa-pkcs1pad.c +1 −1 Original line number Diff line number Diff line Loading @@ -496,7 +496,7 @@ static int pkcs1pad_verify_complete(struct akcipher_request *req, int err) goto done; pos++; if (memcmp(out_buf + pos, digest_info->data, digest_info->size)) if (crypto_memneq(out_buf + pos, digest_info->data, digest_info->size)) goto done; pos += digest_info->size; Loading