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Commit b78c676e authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Gerrit - the friendly Code Review server
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clk: msm: update the fractional divider array for DSI PCLK 



1:1 is the MN divider preference for DSI PCLK for the regular
24 bpp use-case for display as per hardware recommendation.
Update the divider array to give first priority to 1:1
divider combination.

Change-Id: Id4a60093bd88b2cdf8066ae5209cd279d060ea54
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent edae206c

drivers/clk/msm/clock-local2.c

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -1486,8 +1486,8 @@ static int set_rate_pixel(struct clk *clk, unsigned long rate) 
{

	struct rcg_clk *rcg = to_rcg_clk(clk);

	struct clk_freq_tbl *pixel_freq = rcg->current_freq;

	int frac_num[] = {3, 2, 4, 1};

	int frac_den[] = {8, 9, 9, 1};

	int frac_num[] = {1, 3, 2, 4};

	int frac_den[] = {1, 8, 9, 9};

	int delta = 100000;

	int i, rc;