Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b741483d authored by Vitaly Wool's avatar Vitaly Wool Committed by Russell King
Browse files

[ARM] 3623/1: pnx4008: move GPIO-related defines to gpio.h 



Patch from Vitaly Wool

This patch moves GPIO-related defines and static inline funcs from include/asm-arm/arch-pnx4008/pm.h to include/asm-arm/arch-pnx4008/gpio.h.
Also, some more GPIO-related defines are added to include/asm-arm/arch-pnx4008/gpio.h as they are needed for the USB host driver (coming soon...)

Signed-off-by: default avatarVitaly Wool <vwool@ru.mvista.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent e9931b5d

arch/arm/mach-pnx4008/serial.c

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 


#include <linux/serial_core.h>

#include <linux/serial_reg.h>

#include <asm/arch/pm.h>

#include <asm/arch/gpio.h>



#include <asm/arch/clock.h>

include/asm-arm/arch-pnx4008/gpio.h

+102 −0
Original line number Diff line number Diff line
@@ -127,6 +127,79 @@ 
#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))

#define GPIO_ISIN(K)  ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))



/* Start Enable Pin Interrupts - table 58 page 66 */



#define SE_PIN_BASE_INT   32



#define SE_U7_RX_INT            63

#define SE_U7_HCTS_INT          62

#define SE_BT_CLKREQ_INT        61

#define SE_U6_IRRX_INT          60

/*59 unused*/

#define SE_U5_RX_INT            58

#define SE_GPI_11_INT           57

#define SE_U3_RX_INT            56

#define SE_U2_HCTS_INT          55

#define SE_U2_RX_INT            54

#define SE_U1_RX_INT            53

#define SE_DISP_SYNC_INT        52

/*51 unused*/

#define SE_SDIO_INT_N           50

#define SE_MSDIO_START_INT      49

#define SE_GPI_06_INT           48

#define SE_GPI_05_INT           47

#define SE_GPI_04_INT           46

#define SE_GPI_03_INT           45

#define SE_GPI_02_INT           44

#define SE_GPI_01_INT           43

#define SE_GPI_00_INT           42

#define SE_SYSCLKEN_PIN_INT     41

#define SE_SPI1_DATAIN_INT      40

#define SE_GPI_07_INT           39

#define SE_SPI2_DATAIN_INT      38

#define SE_GPI_10_INT           37

#define SE_GPI_09_INT           36

#define SE_GPI_08_INT           35

/*34-32 unused*/



/* Start Enable Internal Interrupts - table 57 page 65 */



#define SE_INT_BASE_INT   0



#define SE_TS_IRQ               31

#define SE_TS_P_INT             30

#define SE_TS_AUX_INT           29

/*27-28 unused*/

#define SE_USB_AHB_NEED_CLK_INT 26

#define SE_MSTIMER_INT          25

#define SE_RTC_INT              24

#define SE_USB_NEED_CLK_INT     23

#define SE_USB_INT              22

#define SE_USB_I2C_INT          21

#define SE_USB_OTG_TIMER_INT    20

#define SE_USB_OTG_ATX_INT_N    19

/*18 unused*/

#define SE_DSP_GPIO4_INT        17

#define SE_KEY_IRQ              16

#define SE_DSP_SLAVEPORT_INT    15

#define SE_DSP_GPIO1_INT        14

#define SE_DSP_GPIO0_INT        13

#define SE_DSP_AHB_INT          12

/*11-6 unused*/

#define SE_GPIO_05_INT          5

#define SE_GPIO_04_INT          4

#define SE_GPIO_03_INT          3

#define SE_GPIO_02_INT          2

#define SE_GPIO_01_INT          1

#define SE_GPIO_00_INT          0



#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))



#define START_INT_ER_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))

#define START_INT_RSR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))

#define START_INT_SR_REG(irq)     IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))

#define START_INT_APR_REG(irq)    IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))



extern int pnx4008_gpio_register_pin(unsigned short pin);

extern int pnx4008_gpio_unregister_pin(unsigned short pin);

extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
@@ -136,4 +209,33 @@ extern int pnx4008_gpio_read_pin_direction(unsigned short pin); 
extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);

extern int pnx4008_gpio_read_pin_mux(unsigned short pin);



static inline void start_int_umask(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |

		     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));

}



static inline void start_int_mask(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &

		     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));

}



static inline void start_int_ack(u8 irq)

{

	__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));

}



static inline void start_int_set_falling_edge(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &

		     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));

}



static inline void start_int_set_rising_edge(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |

		     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));

}



#endif				/* _PNX4008_GPIO_H_ */

include/asm-arm/arch-pnx4008/pm.h

+0 −29
Original line number Diff line number Diff line
@@ -29,34 +29,5 @@ extern void pnx4008_cpu_standby(void); 
extern int pnx4008_startup_pll(struct clk *);

extern int pnx4008_shutdown_pll(struct clk *);



static inline void start_int_umask(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) |

		     START_INT_REG_BIT(irq), START_INT_ER_REG(irq));

}



static inline void start_int_mask(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_ER_REG(irq)) &

		     ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));

}



static inline void start_int_ack(u8 irq)

{

	__raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));

}



static inline void start_int_set_falling_edge(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) &

		     ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));

}



static inline void start_int_set_rising_edge(u8 irq)

{

	__raw_writel(__raw_readl(START_INT_APR_REG(irq)) |

		     START_INT_REG_BIT(irq), START_INT_APR_REG(irq));

}



#endif				/* ASSEMBLER */

#endif				/* __ASM_ARCH_PNX4008_PM_H */