Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b73c798b authored by Lendacky, Thomas's avatar Lendacky, Thomas Committed by David S. Miller
Browse files

amd-xgbe-phy: Checkpatch driver fixes 



This patch contains fixes identified by checkpatch when run with the
strict option.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a2ea14d7

drivers/net/phy/amd-xgbe-phy.c

+0 −4
Original line number Original line Diff line number Diff line
@@ -75,7 +75,6 @@ 
#include <linux/of_device.h>

#include <linux/of_device.h>

#include <linux/uaccess.h>

#include <linux/uaccess.h>







MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");

MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");

MODULE_LICENSE("Dual BSD/GPL");

MODULE_LICENSE("Dual BSD/GPL");

MODULE_VERSION("1.0.0-a");

MODULE_VERSION("1.0.0-a");
@@ -172,7 +171,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver"); 
#define SPEED_1000_TXAMP		0xf

#define SPEED_1000_TXAMP		0xf

#define SPEED_1000_WORD			0x1

#define SPEED_1000_WORD			0x1







/* SerDes RxTx register offsets */

/* SerDes RxTx register offsets */

#define RXTX_REG20			0x0050

#define RXTX_REG20			0x0050

#define RXTX_REG114			0x01c8

#define RXTX_REG114			0x01c8
@@ -266,7 +264,6 @@ do { \ 
	XSIR1_IOWRITE((_priv), _reg, reg_val);				\

	XSIR1_IOWRITE((_priv), _reg, reg_val);				\

} while (0)

} while (0)







/* Macros for reading or writing SerDes RxTx registers

/* Macros for reading or writing SerDes RxTx registers

 *  The ioread macros will get bit fields or full values using the

 *  The ioread macros will get bit fields or full values using the

 *  register definitions formed using the input names

 *  register definitions formed using the input names
@@ -294,7 +291,6 @@ do { \ 
	XRXTX_IOWRITE((_priv), _reg, reg_val);				\

	XRXTX_IOWRITE((_priv), _reg, reg_val);				\

} while (0)

} while (0)







enum amd_xgbe_phy_an {

enum amd_xgbe_phy_an {

	AMD_XGBE_AN_READY = 0,

	AMD_XGBE_AN_READY = 0,

	AMD_XGBE_AN_START,

	AMD_XGBE_AN_START,