Loading drivers/gpu/drm/msm/dsi-staging/dsi_display.c +15 −14 Original line number Diff line number Diff line Loading @@ -3257,20 +3257,6 @@ static int dsi_display_set_mode_sub(struct dsi_display *display, } } for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->phy || !ctrl->ctrl) continue; rc = dsi_phy_set_clk_freq(ctrl->phy, &ctrl->ctrl->clk_freq); if (rc) { pr_err("[%s] failed to set phy clk freq, rc=%d\n", display->name, rc); goto error; } } if (priv_info->phy_timing_len) { for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; Loading Loading @@ -3615,6 +3601,21 @@ static int dsi_display_bind(struct device *dev, pr_info("Successfully bind display panel '%s'\n", display->name); display->drm_dev = drm; for (i = 0; i < display->ctrl_count; i++) { display_ctrl = &display->ctrl[i]; if (!display_ctrl->phy || !display_ctrl->ctrl) continue; rc = dsi_phy_set_clk_freq(display_ctrl->phy, &display_ctrl->ctrl->clk_freq); if (rc) { pr_err("[%s] failed to set phy clk freq, rc=%d\n", display->name, rc); goto error; } } /* Initialize resources for continuous splash */ rc = dsi_display_splash_res_init(display); if (rc) Loading drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +1 −1 Original line number Diff line number Diff line Loading @@ -663,7 +663,7 @@ int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable) } } } else { if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_ON && if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF && dsi_phy->regulator_required) { rc = dsi_pwr_enable_regulator( &dsi_phy->pwr_info.phy_pwr, false); Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_display.c +15 −14 Original line number Diff line number Diff line Loading @@ -3257,20 +3257,6 @@ static int dsi_display_set_mode_sub(struct dsi_display *display, } } for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; if (!ctrl->phy || !ctrl->ctrl) continue; rc = dsi_phy_set_clk_freq(ctrl->phy, &ctrl->ctrl->clk_freq); if (rc) { pr_err("[%s] failed to set phy clk freq, rc=%d\n", display->name, rc); goto error; } } if (priv_info->phy_timing_len) { for (i = 0; i < display->ctrl_count; i++) { ctrl = &display->ctrl[i]; Loading Loading @@ -3615,6 +3601,21 @@ static int dsi_display_bind(struct device *dev, pr_info("Successfully bind display panel '%s'\n", display->name); display->drm_dev = drm; for (i = 0; i < display->ctrl_count; i++) { display_ctrl = &display->ctrl[i]; if (!display_ctrl->phy || !display_ctrl->ctrl) continue; rc = dsi_phy_set_clk_freq(display_ctrl->phy, &display_ctrl->ctrl->clk_freq); if (rc) { pr_err("[%s] failed to set phy clk freq, rc=%d\n", display->name, rc); goto error; } } /* Initialize resources for continuous splash */ rc = dsi_display_splash_res_init(display); if (rc) Loading
drivers/gpu/drm/msm/dsi-staging/dsi_phy.c +1 −1 Original line number Diff line number Diff line Loading @@ -663,7 +663,7 @@ int dsi_phy_set_power_state(struct msm_dsi_phy *dsi_phy, bool enable) } } } else { if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_ON && if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF && dsi_phy->regulator_required) { rc = dsi_pwr_enable_regulator( &dsi_phy->pwr_info.phy_pwr, false); Loading