Loading drivers/usb/host/xhci-hub.c +7 −9 Original line number Diff line number Diff line Loading @@ -867,18 +867,18 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, case USB_PORT_FEAT_U1_TIMEOUT: if (hcd->speed != HCD_USB3) goto error; temp = xhci_readl(xhci, port_array[wIndex] + 1); temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); temp &= ~PORT_U1_TIMEOUT_MASK; temp |= PORT_U1_TIMEOUT(timeout); xhci_writel(xhci, temp, port_array[wIndex] + 1); xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); break; case USB_PORT_FEAT_U2_TIMEOUT: if (hcd->speed != HCD_USB3) goto error; temp = xhci_readl(xhci, port_array[wIndex] + 1); temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); temp &= ~PORT_U2_TIMEOUT_MASK; temp |= PORT_U2_TIMEOUT(timeout); xhci_writel(xhci, temp, port_array[wIndex] + 1); xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); break; default: goto error; Loading Loading @@ -1098,10 +1098,8 @@ int xhci_bus_suspend(struct usb_hcd *hcd) __le32 __iomem *addr; u32 tmp; /* Add one to the port status register address to get * the port power control register address. */ addr = port_array[port_index] + 1; /* Get the port power control register address. */ addr = port_array[port_index] + PORTPMSC; tmp = xhci_readl(xhci, addr); tmp |= PORT_RWE; xhci_writel(xhci, tmp, addr); Loading Loading @@ -1193,7 +1191,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) /* Add one to the port status register address to get * the port power control register address. */ addr = port_array[port_index] + 1; addr = port_array[port_index] + PORTPMSC; tmp = xhci_readl(xhci, addr); tmp &= ~PORT_RWE; xhci_writel(xhci, tmp, addr); Loading drivers/usb/host/xhci.c +2 −2 Original line number Diff line number Diff line Loading @@ -3911,7 +3911,7 @@ static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd, * Check device's USB 2.0 extension descriptor to determine whether * HIRD or BESL shoule be used. See USB2.0 LPM errata. */ pm_addr = port_array[port_num] + 1; pm_addr = port_array[port_num] + PORTPMSC; hird = xhci_calculate_hird_besl(xhci, udev); temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird); xhci_writel(xhci, temp, pm_addr); Loading Loading @@ -4009,7 +4009,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, port_array = xhci->usb2_ports; port_num = udev->portnum - 1; pm_addr = port_array[port_num] + 1; pm_addr = port_array[port_num] + PORTPMSC; temp = xhci_readl(xhci, pm_addr); xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", Loading drivers/usb/host/xhci.h +5 −0 Original line number Diff line number Diff line Loading @@ -132,6 +132,11 @@ struct xhci_cap_regs { /* Number of registers per port */ #define NUM_PORT_REGS 4 #define PORTSC 0 #define PORTPMSC 1 #define PORTLI 2 #define PORTHLPMC 3 /** * struct xhci_op_regs - xHCI Host Controller Operational Registers. * @command: USBCMD - xHC command register Loading Loading
drivers/usb/host/xhci-hub.c +7 −9 Original line number Diff line number Diff line Loading @@ -867,18 +867,18 @@ int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, case USB_PORT_FEAT_U1_TIMEOUT: if (hcd->speed != HCD_USB3) goto error; temp = xhci_readl(xhci, port_array[wIndex] + 1); temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); temp &= ~PORT_U1_TIMEOUT_MASK; temp |= PORT_U1_TIMEOUT(timeout); xhci_writel(xhci, temp, port_array[wIndex] + 1); xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); break; case USB_PORT_FEAT_U2_TIMEOUT: if (hcd->speed != HCD_USB3) goto error; temp = xhci_readl(xhci, port_array[wIndex] + 1); temp = xhci_readl(xhci, port_array[wIndex] + PORTPMSC); temp &= ~PORT_U2_TIMEOUT_MASK; temp |= PORT_U2_TIMEOUT(timeout); xhci_writel(xhci, temp, port_array[wIndex] + 1); xhci_writel(xhci, temp, port_array[wIndex] + PORTPMSC); break; default: goto error; Loading Loading @@ -1098,10 +1098,8 @@ int xhci_bus_suspend(struct usb_hcd *hcd) __le32 __iomem *addr; u32 tmp; /* Add one to the port status register address to get * the port power control register address. */ addr = port_array[port_index] + 1; /* Get the port power control register address. */ addr = port_array[port_index] + PORTPMSC; tmp = xhci_readl(xhci, addr); tmp |= PORT_RWE; xhci_writel(xhci, tmp, addr); Loading Loading @@ -1193,7 +1191,7 @@ int xhci_bus_resume(struct usb_hcd *hcd) /* Add one to the port status register address to get * the port power control register address. */ addr = port_array[port_index] + 1; addr = port_array[port_index] + PORTPMSC; tmp = xhci_readl(xhci, addr); tmp &= ~PORT_RWE; xhci_writel(xhci, tmp, addr); Loading
drivers/usb/host/xhci.c +2 −2 Original line number Diff line number Diff line Loading @@ -3911,7 +3911,7 @@ static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd, * Check device's USB 2.0 extension descriptor to determine whether * HIRD or BESL shoule be used. See USB2.0 LPM errata. */ pm_addr = port_array[port_num] + 1; pm_addr = port_array[port_num] + PORTPMSC; hird = xhci_calculate_hird_besl(xhci, udev); temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird); xhci_writel(xhci, temp, pm_addr); Loading Loading @@ -4009,7 +4009,7 @@ int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd, port_array = xhci->usb2_ports; port_num = udev->portnum - 1; pm_addr = port_array[port_num] + 1; pm_addr = port_array[port_num] + PORTPMSC; temp = xhci_readl(xhci, pm_addr); xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n", Loading
drivers/usb/host/xhci.h +5 −0 Original line number Diff line number Diff line Loading @@ -132,6 +132,11 @@ struct xhci_cap_regs { /* Number of registers per port */ #define NUM_PORT_REGS 4 #define PORTSC 0 #define PORTPMSC 1 #define PORTLI 2 #define PORTHLPMC 3 /** * struct xhci_op_regs - xHCI Host Controller Operational Registers. * @command: USBCMD - xHC command register Loading