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Commit b6d95c44 authored by Siva Kumar Akkireddi's avatar Siva Kumar Akkireddi Committed by Gerrit - the friendly Code Review server
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msm: ep_pcie: Correct L1ss register offsets 



Update the correct L1ss capability and control register offsets

Change-Id: Iebced7adc022821183b2dbb952fa4d2e4fe9b332
Signed-off-by: default avatarSiva Kumar Akkireddi <sivaa@codeaurora.org>
parent fc52b640

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -90,8 +90,8 @@ 
#define PCIE20_CAP_LINKCTRLSTATUS      0x80

#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98

#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0

#define PCIE20_L1SUB_CAPABILITY        0x154

#define PCIE20_L1SUB_CONTROL1          0x158

#define PCIE20_L1SUB_CAPABILITY        0x1E0

#define PCIE20_L1SUB_CONTROL1          0x1E4

#define PCIE20_ACK_F_ASPM_CTRL_REG     0x70C

#define PCIE20_MASK_ACK_N_FTS          0xff00

#define PCIE20_MISC_CONTROL_1          0x8BC