clk: qcom: mdss: Fix DSI clock divider configuration

Adjusting the MND ordering and the DSI clock tree configuration
to match recommendation. When setting DSI pixel clock rate,
the MND array is ordered in a way that the requested rate
goes from highest to lowest. Since the recommendation is to
divide the clocks as close to VCO as possible, the request
should be from lowest to highest. So reversing the fraction
array to match the recommendation. The DSI clock tree is
modified to include the pll output divider and limit the
VCO post div ratios to 1 and 4 only.

Change-Id: I6b8f5cc96eaf2e9a263b92788f5626bbfbdea8b1
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>