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Commit b67360db authored by Chris Zankel's avatar Chris Zankel
Browse files

[XTENSA] Flush the page-address in update-mmu instead of user-address 



The TLB entry for the user address doesn't exist at the time we
want to flush the caches, so use the page address. Note that processor
configurations with cache-aliasing issues are treated separately.

Signed-off-by: default avatarChris Zankel <chris@zankel.net>
parent 49883224

arch/xtensa/mm/cache.c

+3 −3
Original line number Diff line number Diff line
@@ -180,9 +180,9 @@ update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte) 
#else

	if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)

	    && (vma->vm_flags & VM_EXEC) != 0) {

		unsigned long vaddr = addr & PAGE_MASK;

		__flush_dcache_page(vaddr);

		__invalidate_icache_page(vaddr);

	    	unsigned long paddr = (unsigned long) page_address(page);

		__flush_dcache_page(paddr);

		__invalidate_icache_page(paddr);

		set_bit(PG_arch_1, &page->flags);

	}

#endif