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Commit b63b4b45 authored by Maria Dimakopoulou's avatar Maria Dimakopoulou Committed by Ingo Molnar
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perf/x86/intel: Enforce HT bug workaround with PEBS for SNB/IVB/HSW 



This patch modifies the PEBS constraint tables for SNB/IVB/HSW
such that corrupting events supporting PEBS activate the HT
workaround.

Signed-off-by: default avatarMaria Dimakopoulou <maria.n.dimakopoulou@gmail.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: default avatarStephane Eranian <eranian@google.com>
Cc: bp@alien8.de
Cc: jolsa@redhat.com
Cc: kan.liang@intel.com
Link: http://lkml.kernel.org/r/1416251225-17721-9-git-send-email-eranian@google.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 93fcf72c

arch/x86/kernel/cpu/perf_event.h

+19 −1
Original line number Diff line number Diff line
@@ -330,18 +330,36 @@ struct cpu_hw_events { 
			  ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)



#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \

	__EVENT_CONSTRAINT(code, n,			\

			  ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, \

			  PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)



/* Check flags and event code/umask, and set the HSW store flag */

#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \

	__EVENT_CONSTRAINT(code, n, 			\

			  INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)



#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \

	__EVENT_CONSTRAINT(code, n,			\

			  INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, \

			  PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)



/* Check flags and event code/umask, and set the HSW load flag */

#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \

	__EVENT_CONSTRAINT(code, n, 			\

			  INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)



#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \

	__EVENT_CONSTRAINT(code, n,			\

			  INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \

			  HWEIGHT(n), 0, \

			  PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)



/* Check flags and event code/umask, and set the HSW N/A flag */

#define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \

	__EVENT_CONSTRAINT(code, n, 			\

arch/x86/kernel/cpu/perf_event_intel_ds.c

+18 −10
Original line number Diff line number Diff line
@@ -612,6 +612,10 @@ struct event_constraint intel_snb_pebs_event_constraints[] = { 
	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */

	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */

	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),

        INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */

        INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */

        INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */

        INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */

	/* Allow all events as PEBS with no flags */

	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),

	EVENT_CONSTRAINT_END
@@ -623,6 +627,10 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = { 
	INTEL_PST_CONSTRAINT(0x02cd, 0x8),    /* MEM_TRANS_RETIRED.PRECISE_STORES */

	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */

	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),

	INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),    /* MEM_UOP_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),    /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */

	INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),    /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */

	/* Allow all events as PEBS with no flags */

	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),

        EVENT_CONSTRAINT_END
@@ -634,16 +642,16 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = { 
	/* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */

	INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */

	INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),    /* MEM_LOAD_UOPS_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),    /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */

	INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),    /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */

	/* Allow all events as PEBS with no flags */

	INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),

	EVENT_CONSTRAINT_END