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Commit b61e6f8c authored by Tengfei Fan's avatar Tengfei Fan
Browse files

arm32: Potential rollover condition for timer counter 



There is potential rollover condition for CNTVCT and
CNTPCT counters. So on any architecture timer counter
read, if the least significant 32 bits are set,
reread counter.

Change-Id: Iacc482ad956d5589d59a2a111576ec0463f5a1bb
Signed-off-by: default avatarTengfei Fan <tengfeif@codeaurora.org>
parent e56c1c5c

arch/arm/include/asm/arch_timer.h

+7 −0
Original line number Diff line number Diff line
@@ -92,7 +92,14 @@ static inline u64 arch_counter_get_cntvct(void) 
	u64 cval;



	isb();

#if IS_ENABLED(CONFIG_MSM_TIMER_LEAP)

#define L32_BITS	0x00000000FFFFFFFF

	do {

		asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));

	} while ((cval & L32_BITS) == L32_BITS);

#else

	asm volatile("mrrc p15, 1, %Q0, %R0, c14" : "=r" (cval));

#endif

	return cval;

}

drivers/clocksource/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -334,7 +334,7 @@ config ARM_ARCH_TIMER_VCT_ACCESS 
config MSM_TIMER_LEAP

	bool "ARCH TIMER counter rollover"

	default n

	depends on ARM_ARCH_TIMER && ARM64

	depends on ARM_ARCH_TIMER

	help

	  This option enables a check for least significant 32 bits of

	  counter rollover. On every counter read if least significant