Merge "clk: mdss: remove configuring phy registers during pll disable" into msm-4.8 (b618ef0e) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/mdss/mdss-dsi-pll-8996-util.c

+0 −16

Original line number	Diff line number	Diff line
		@@ -295,22 +295,6 @@ static void dsi_pll_disable(struct clk *c)

		dsi_pll_stop_8996(pll->pll_base);

		/* stop pll output */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
		/* stop clk */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
		/* stop digital block */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);

		if (slave) {
		/* stop pll output */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0);
		/* stop clk */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0);
		/* stop digital block */
		MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0);
		}

		mdss_pll_resource_enable(pll, false);

		pll->pll_on = false;