Merge branch 'for_2.6.34_b' of git://git.pwsan.com/linux-2.6 into omap-for-linus (b610ec50) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/configs/omap_4430sdp_defconfig

+4 −3

Original line number	Diff line number	Diff line
		@@ -199,7 +199,7 @@ CONFIG_ARCH_OMAP4=y
		#
		# CONFIG_OMAP_RESET_CLOCKS is not set
		# CONFIG_OMAP_MUX is not set
		# CONFIG_OMAP_MCBSP is not set
		CONFIG_OMAP_MCBSP=y
		# CONFIG_OMAP_MBOX_FWK is not set
		# CONFIG_OMAP_MPU_TIMER is not set
		CONFIG_OMAP_32K_TIMER=y
		@@ -304,7 +304,7 @@ CONFIG_ALIGNMENT_TRAP=y
		#
		CONFIG_ZBOOT_ROM_TEXT=0x0
		CONFIG_ZBOOT_ROM_BSS=0x0
		CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
		CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS2,115200n8 initrd=0x81600000,20M ramdisk_size=20480"
		# CONFIG_XIP_KERNEL is not set
		# CONFIG_KEXEC is not set

		@@ -488,7 +488,8 @@ CONFIG_GPIOLIB=y
		# CONFIG_POWER_SUPPLY is not set
		# CONFIG_HWMON is not set
		# CONFIG_THERMAL is not set
		# CONFIG_WATCHDOG is not set
		CONFIG_WATCHDOG=y
		CONFIG_OMAP_WATCHDOG=y
		CONFIG_SSB_POSSIBLE=y

		#

arch/arm/mach-omap1/clock.c

+1 −18

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/mach-omap1/clock.c
		*
		* Copyright (C) 2004 - 2005, 2009 Nokia corporation
		* Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
		* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
		*
		* Modified to use omap shared clock framework by
		@@ -38,20 +38,6 @@ struct clk api_ck_p, ck_dpll1_p, *ck_ref_p;
		* Omap1 specific clock functions
		-------------------------------------------------------------------------/

		static int clk_omap1_dummy_enable(struct clk *clk)
		{
		return 0;
		}

		static void clk_omap1_dummy_disable(struct clk *clk)
		{
		}

		const struct clkops clkops_dummy = {
		.enable = clk_omap1_dummy_enable,
		.disable = clk_omap1_dummy_disable,
		};

		unsigned long omap1_uart_recalc(struct clk *clk)
		{
		unsigned int val = __raw_readl(clk->enable_reg);
		@@ -571,9 +557,6 @@ const struct clkops clkops_uart = {

		long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
		{
		if (clk->flags & RATE_FIXED)
		return clk->rate;

		if (clk->round_rate != NULL)
		return clk->round_rate(clk, rate);

arch/arm/mach-omap1/clock_data.c

+12 −29

Original line number	Diff line number	Diff line
		/*
		* linux/arch/arm/mach-omap1/clock_data.c
		*
		* Copyright (C) 2004 - 2005, 2009 Nokia corporation
		* Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
		* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
		* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
		*
		@@ -27,13 +27,6 @@
		* Omap1 clocks
		-------------------------------------------------------------------------/

		/* XXX is this necessary? */
		static struct clk dummy_ck = {
		.name = "dummy",
		.ops = &clkops_dummy,
		.flags = RATE_FIXED,
		};

		static struct clk ck_ref = {
		.name = "ck_ref",
		.ops = &clkops_null,
		@@ -389,8 +382,7 @@ static struct uart_clk uart1_16xx = {
		/* Direct from ULPD, no real parent */
		.parent = &armper_ck.clk,
		.rate = 48000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT \|
		CLOCK_NO_IDLE_PARENT,
		.flags = ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
		.enable_bit = 29,
		},
		@@ -430,8 +422,7 @@ static struct uart_clk uart3_16xx = {
		/* Direct from ULPD, no real parent */
		.parent = &armper_ck.clk,
		.rate = 48000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT \|
		CLOCK_NO_IDLE_PARENT,
		.flags = ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
		.enable_bit = 31,
		},
		@@ -443,7 +434,7 @@ static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent */
		.rate = 6000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT,
		.flags = ENABLE_REG_32BIT,
		.enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
		.enable_bit = USB_MCLK_EN_BIT,
		};
		@@ -453,7 +444,7 @@ static struct clk usb_hhc_ck1510 = {
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent */
		.rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
		.flags = RATE_FIXED \| ENABLE_REG_32BIT,
		.flags = ENABLE_REG_32BIT,
		.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
		.enable_bit = USB_HOST_HHC_UHOST_EN,
		};
		@@ -464,7 +455,7 @@ static struct clk usb_hhc_ck16xx = {
		/* Direct from ULPD, no parent */
		.rate = 48000000,
		/* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
		.flags = RATE_FIXED \| ENABLE_REG_32BIT,
		.flags = ENABLE_REG_32BIT,
		.enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
		.enable_bit = 8 /* UHOST_EN */,
		};
		@@ -474,7 +465,6 @@ static struct clk usb_dc_ck = {
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent */
		.rate = 48000000,
		.flags = RATE_FIXED,
		.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
		.enable_bit = 4,
		};
		@@ -484,7 +474,6 @@ static struct clk usb_dc_ck7xx = {
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent */
		.rate = 48000000,
		.flags = RATE_FIXED,
		.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
		.enable_bit = 8,
		};
		@@ -494,7 +483,6 @@ static struct clk mclk_1510 = {
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent. May be enabled by ext hardware. */
		.rate = 12000000,
		.flags = RATE_FIXED,
		.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
		.enable_bit = 6,
		};
		@@ -515,7 +503,6 @@ static struct clk bclk_1510 = {
		.ops = &clkops_generic,
		/* Direct from ULPD, no parent. May be enabled by ext hardware. */
		.rate = 12000000,
		.flags = RATE_FIXED,
		};

		static struct clk bclk_16xx = {
		@@ -530,36 +517,34 @@ static struct clk bclk_16xx = {
		};

		static struct clk mmc1_ck = {
		.name = "mmc_ck",
		.name = "mmc1_ck",
		.ops = &clkops_generic,
		/* Functional clock is direct from ULPD, interface clock is ARMPER */
		.parent = &armper_ck.clk,
		.rate = 48000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.flags = ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
		.enable_bit = 23,
		};

		static struct clk mmc2_ck = {
		.name = "mmc_ck",
		.id = 1,
		.name = "mmc2_ck",
		.ops = &clkops_generic,
		/* Functional clock is direct from ULPD, interface clock is ARMPER */
		.parent = &armper_ck.clk,
		.rate = 48000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.flags = ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
		.enable_bit = 20,
		};

		static struct clk mmc3_ck = {
		.name = "mmc_ck",
		.id = 2,
		.name = "mmc3_ck",
		.ops = &clkops_generic,
		/* Functional clock is direct from ULPD, interface clock is ARMPER */
		.parent = &armper_ck.clk,
		.rate = 48000000,
		.flags = RATE_FIXED \| ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.flags = ENABLE_REG_32BIT \| CLOCK_NO_IDLE_PARENT,
		.enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
		.enable_bit = 12,
		};
		@@ -577,7 +562,6 @@ static struct clk virtual_ck_mpu = {
		remains active during MPU idle whenever this is enabled */
		static struct clk i2c_fck = {
		.name = "i2c_fck",
		.id = 1,
		.ops = &clkops_null,
		.flags = CLOCK_NO_IDLE_PARENT,
		.parent = &armxor_ck.clk,
		@@ -586,7 +570,6 @@ static struct clk i2c_fck = {

		static struct clk i2c_ick = {
		.name = "i2c_ick",
		.id = 1,
		.ops = &clkops_null,
		.flags = CLOCK_NO_IDLE_PARENT,
		.parent = &armper_ck.clk,

arch/arm/mach-omap2/Makefile

+29 −18

Original line number	Diff line number	Diff line
		@@ -5,23 +5,17 @@
		# Common support
		obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o

		omap-2-3-common = irq.o sdrc.o omap_hwmod.o
		omap-3-4-common = dpll3xxx.o
		omap-2-3-common = irq.o sdrc.o
		hwmod-common = omap_hwmod.o \
		omap_hwmod_common_data.o
		prcm-common = prcm.o powerdomain.o
		clock-common = clock.o clock_common_data.o \
		clockdomain.o clkt_dpll.o \
		clkt_clksel.o
		clock-omap2xxx = clkt2xxx_dpllcore.o \
		clkt2xxx_virt_prcm_set.o \
		clkt2xxx_apll.o clkt2xxx_osc.o \
		clkt2xxx_sys.o
		clock-omap3xxx = clkt34xx_dpll3m2.o

		obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
		$(clock-omap2xxx)
		obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
		$(omap-3-4-common) $(clock-omap3xxx)
		obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) $(prcm-common) $(clock-common)
		obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
		obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(hwmod-common)
		obj-$(CONFIG_ARCH_OMAP4) += $(prcm-common)

		obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

		@@ -63,11 +57,28 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
		obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o

		# Clock framework
		obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
		obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o \
		clkt2xxx_sys.o \
		clkt2xxx_dpllcore.o \
		clkt2xxx_virt_prcm_set.o \
		clkt2xxx_apll.o clkt2xxx_osc.o
		obj-$(CONFIG_ARCH_OMAP2420) += clock2420_data.o
		obj-$(CONFIG_ARCH_OMAP2430) += clock2430.o clock2430_data.o
		obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o \
		clock34xx.o clkt34xx_dpll3m2.o \
		clock3517.o clock36xx.o \
		dpll3xxx.o clock3xxx_data.o
		obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o \
		dpll3xxx.o

		# OMAP2 clock rate set data (old "OPP" data)
		obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
		obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
		obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
		obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o

		# hwmod data
		obj-$(CONFIG_ARCH_OMAP2420) += omap_hwmod_2420_data.o
		obj-$(CONFIG_ARCH_OMAP2430) += omap_hwmod_2430_data.o
		obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o

		# EMU peripherals
		obj-$(CONFIG_OMAP3_EMU) += emu.o

arch/arm/mach-omap2/clkt2xxx_apll.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -38,6 +38,8 @@
		#define APLLS_CLKIN_13MHZ 2
		#define APLLS_CLKIN_12MHZ 3

		void __iomem *cm_idlest_pll;

		/* Private functions */

		/* Enable an APLL if off */
		@@ -56,8 +58,8 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
		cval \|= apll_mask;
		cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);

		omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), status_mask,
		clk->name);
		omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
		OMAP24XX_CM_IDLEST_VAL, clk->name);

		/*
		* REVISIT: Should we return an error code if omap2_wait_clock_ready()