Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b60decad authored by Maxime Ripard's avatar Maxime Ripard Committed by Olof Johansson
Browse files

sunxi: Cleanup the reset code and add meaningful registers defines 



Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent b28eaacf

arch/arm/mach-sunxi/sunxi.c

+15 −4
Original line number Diff line number Diff line
@@ -27,7 +27,10 @@ 
#include "sunxi.h"



#define WATCHDOG_CTRL_REG	0x00

#define WATCHDOG_CTRL_RESTART		(1 << 0)

#define WATCHDOG_MODE_REG	0x04

#define WATCHDOG_MODE_ENABLE		(1 << 0)

#define WATCHDOG_MODE_RESET_ENABLE	(1 << 1)



static void __iomem *wdt_base;
@@ -48,11 +51,19 @@ static void sunxi_restart(char mode, const char *cmd) 
		return;



	/* Enable timer and set reset bit in the watchdog */

	writel(3, wdt_base + WATCHDOG_MODE_REG);

	writel(0xa57 << 1 | 1, wdt_base + WATCHDOG_CTRL_REG);

	writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,

		wdt_base + WATCHDOG_MODE_REG);



	/*

	 * Restart the watchdog. The default (and lowest) interval

	 * value for the watchdog is 0.5s.

	 */

	writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);



	while (1) {

		mdelay(5);

		writel(3, wdt_base + WATCHDOG_MODE_REG);

		writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,

			wdt_base + WATCHDOG_MODE_REG);

	}

}