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Commit b5591bd6 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux into drm-fixes 

- fix a resume hang on mullins
- fix an oops on module unload with vgaswitcheroo (radeon and nouveau)
- fix possible hangs DMA engine hangs due to hw bugs

* 'drm-fixes-3.17' of git://people.freedesktop.org/~agd5f/linux:
  drm/nouveau/runpm: fix module unload
  drm/radeon/px: fix module unload
  vgaswitcheroo: add vga_switcheroo_fini_domain_pm_ops
  drm/radeon: don't reset dma on r6xx-evergreen init
  drm/radeon: don't reset sdma on CIK init
  drm/radeon: don't reset dma on NI/SI init
  drm/radeon/dpm: fix resume on mullins
  drm/radeon: Disable HDP flush before every CS again for < r600
  drm/radeon: delete unused PTE_* defines
parents 7dc9250f 53beaa01

drivers/gpu/drm/nouveau/nouveau_vga.c

+9 −0
Original line number Diff line number Diff line
@@ -108,7 +108,16 @@ void 
nouveau_vga_fini(struct nouveau_drm *drm)

{

	struct drm_device *dev = drm->dev;

	bool runtime = false;



	if (nouveau_runtime_pm == 1)

		runtime = true;

	if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm()))

		runtime = true;



	vga_switcheroo_unregister_client(dev->pdev);

	if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus())

		vga_switcheroo_fini_domain_pm_ops(drm->dev->dev);

	vga_client_register(dev->pdev, NULL, NULL, NULL);

}

drivers/gpu/drm/radeon/cik_sdma.c

+0 −7
Original line number Diff line number Diff line
@@ -489,13 +489,6 @@ int cik_sdma_resume(struct radeon_device *rdev) 
{

	int r;



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);

	RREG32(SRBM_SOFT_RESET);



	r = cik_sdma_load_microcode(rdev);

	if (r)

		return r;

drivers/gpu/drm/radeon/kv_dpm.c

+21 −7
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 
#define KV_MINIMUM_ENGINE_CLOCK         800

#define SMC_RAM_END                     0x40000



static int kv_enable_nb_dpm(struct radeon_device *rdev,

			    bool enable);

static void kv_init_graphics_levels(struct radeon_device *rdev);

static int kv_calculate_ds_divider(struct radeon_device *rdev);

static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
@@ -1295,6 +1297,9 @@ void kv_dpm_disable(struct radeon_device *rdev) 
{

	kv_smc_bapm_enable(rdev, false);



	if (rdev->family == CHIP_MULLINS)

		kv_enable_nb_dpm(rdev, false);



	/* powerup blocks */

	kv_dpm_powergate_acp(rdev, false);

	kv_dpm_powergate_samu(rdev, false);
@@ -1769,16 +1774,25 @@ static int kv_update_dfs_bypass_settings(struct radeon_device *rdev, 
	return ret;

}



static int kv_enable_nb_dpm(struct radeon_device *rdev)

static int kv_enable_nb_dpm(struct radeon_device *rdev,

			    bool enable)

{

	struct kv_power_info *pi = kv_get_pi(rdev);

	int ret = 0;



	if (enable) {

		if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {

			ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);

			if (ret == 0)

				pi->nb_dpm_enabled = true;

		}

	} else {

		if (pi->enable_nb_dpm && pi->nb_dpm_enabled) {

			ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Disable);

			if (ret == 0)

				pi->nb_dpm_enabled = false;

		}

	}



	return ret;

}
@@ -1864,7 +1878,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev) 
			}

			kv_update_sclk_t(rdev);

			if (rdev->family == CHIP_MULLINS)

				kv_enable_nb_dpm(rdev);

				kv_enable_nb_dpm(rdev, true);

		}

	} else {

		if (pi->enable_dpm) {
@@ -1889,7 +1903,7 @@ int kv_dpm_set_power_state(struct radeon_device *rdev) 
			}

			kv_update_acp_boot_level(rdev);

			kv_update_sclk_t(rdev);

			kv_enable_nb_dpm(rdev);

			kv_enable_nb_dpm(rdev, true);

		}

	}

drivers/gpu/drm/radeon/ni_dma.c

+0 −6
Original line number Diff line number Diff line
@@ -191,12 +191,6 @@ int cayman_dma_resume(struct radeon_device *rdev) 
	u32 reg_offset, wb_offset;

	int i, r;



	/* Reset dma */

	WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);

	RREG32(SRBM_SOFT_RESET);

	udelay(50);

	WREG32(SRBM_SOFT_RESET, 0);



	for (i = 0; i < 2; i++) {

		if (i == 0) {

			ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];

drivers/gpu/drm/radeon/r100.c

+14 −14
Original line number Diff line number Diff line
@@ -821,6 +821,20 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) 
		return RREG32(RADEON_CRTC2_CRNT_FRAME);

}



/**

 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer

 * rdev: radeon device structure

 * ring: ring buffer struct for emitting packets

 */

static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)

{

	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |

				RADEON_HDP_READ_BUFFER_INVALIDATE);

	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);

}



/* Who ever call radeon_fence_emit should call ring_lock and ask

 * for enough space (today caller are ib schedule and buffer move) */

void r100_fence_ring_emit(struct radeon_device *rdev,
@@ -1056,20 +1070,6 @@ void r100_gfx_set_wptr(struct radeon_device *rdev, 
	(void)RREG32(RADEON_CP_RB_WPTR);

}



/**

 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer

 * rdev: radeon device structure

 * ring: ring buffer struct for emitting packets

 */

void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)

{

	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

	radeon_ring_write(ring, rdev->config.r100.hdp_cntl |

				RADEON_HDP_READ_BUFFER_INVALIDATE);

	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));

	radeon_ring_write(ring, rdev->config.r100.hdp_cntl);

}



static void r100_cp_load_microcode(struct radeon_device *rdev)

{

	const __be32 *fw_data;