Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b5321f30 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Unify intel_logical_ring_emit and intel_ring_emit 



Both perform the same actions with more or less indirection, so just
unify the code.

v2: Add back a few intel_engine_cs locals

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1469432687-22756-11-git-send-email-chris@chris-wilson.co.uk
Link: http://patchwork.freedesktop.org/patch/msgid/1470174640-18242-1-git-send-email-chris@chris-wilson.co.uk
parent f2dd7578

drivers/gpu/drm/i915/i915_gem_context.c

+24 −23
Original line number Diff line number Diff line
@@ -552,6 +552,7 @@ static inline int 
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)

{

	struct drm_i915_private *dev_priv = req->i915;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_engine_cs *engine = req->engine;

	u32 flags = hw_flags | MI_MM_SPACE_GTT;

	const int num_rings =
@@ -589,64 +590,64 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) 


	/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */

	if (INTEL_GEN(dev_priv) >= 7) {

		intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);

		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);

		if (num_rings) {

			struct intel_engine_cs *signaller;



			intel_ring_emit(engine,

			intel_ring_emit(ring,

					MI_LOAD_REGISTER_IMM(num_rings));

			for_each_engine(signaller, dev_priv) {

				if (signaller == engine)

					continue;



				intel_ring_emit_reg(engine,

				intel_ring_emit_reg(ring,

						    RING_PSMI_CTL(signaller->mmio_base));

				intel_ring_emit(engine,

				intel_ring_emit(ring,

						_MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));

			}

		}

	}



	intel_ring_emit(engine, MI_NOOP);

	intel_ring_emit(engine, MI_SET_CONTEXT);

	intel_ring_emit(engine,

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_emit(ring, MI_SET_CONTEXT);

	intel_ring_emit(ring,

			i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |

			flags);

	/*

	 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP

	 * WaMiSetContext_Hang:snb,ivb,vlv

	 */

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_emit(ring, MI_NOOP);



	if (INTEL_GEN(dev_priv) >= 7) {

		if (num_rings) {

			struct intel_engine_cs *signaller;

			i915_reg_t last_reg = {}; /* keep gcc quiet */



			intel_ring_emit(engine,

			intel_ring_emit(ring,

					MI_LOAD_REGISTER_IMM(num_rings));

			for_each_engine(signaller, dev_priv) {

				if (signaller == engine)

					continue;



				last_reg = RING_PSMI_CTL(signaller->mmio_base);

				intel_ring_emit_reg(engine, last_reg);

				intel_ring_emit(engine,

				intel_ring_emit_reg(ring, last_reg);

				intel_ring_emit(ring,

						_MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));

			}



			/* Insert a delay before the next switch! */

			intel_ring_emit(engine,

			intel_ring_emit(ring,

					MI_STORE_REGISTER_MEM |

					MI_SRM_LRM_GLOBAL_GTT);

			intel_ring_emit_reg(engine, last_reg);

			intel_ring_emit(engine, engine->scratch.gtt_offset);

			intel_ring_emit(engine, MI_NOOP);

			intel_ring_emit_reg(ring, last_reg);

			intel_ring_emit(ring, engine->scratch.gtt_offset);

			intel_ring_emit(ring, MI_NOOP);

		}

		intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE);

		intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);

	}



	intel_ring_advance(engine);

	intel_ring_advance(ring);



	return ret;

}
@@ -654,7 +655,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags) 
static int remap_l3(struct drm_i915_gem_request *req, int slice)

{

	u32 *remap_info = req->i915->l3_parity.remap_info[slice];

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	int i, ret;



	if (!remap_info)
@@ -669,13 +670,13 @@ static int remap_l3(struct drm_i915_gem_request *req, int slice) 
	 * here because no other code should access these registers other than

	 * at initialization time.

	 */

	intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));

	for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {

		intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));

		intel_ring_emit(engine, remap_info[i]);

		intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));

		intel_ring_emit(ring, remap_info[i]);

	}

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_advance(engine);

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);



	return 0;

}

drivers/gpu/drm/i915/i915_gem_execbuffer.c

+24 −29
Original line number Diff line number Diff line
@@ -1171,14 +1171,12 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) 
}



static int

i915_reset_gen7_sol_offsets(struct drm_device *dev,

			    struct drm_i915_gem_request *req)

i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)

{

	struct intel_engine_cs *engine = req->engine;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_ringbuffer *ring = req->ringbuf;

	int ret, i;



	if (!IS_GEN7(dev) || engine != &dev_priv->engine[RCS]) {

	if (!IS_GEN7(req->i915) || req->engine->id != RCS) {

		DRM_DEBUG("sol reset is gen7/rcs only\n");

		return -EINVAL;

	}
@@ -1188,12 +1186,12 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev, 
		return ret;



	for (i = 0; i < 4; i++) {

		intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(engine, GEN7_SO_WRITE_OFFSET(i));

		intel_ring_emit(engine, 0);

		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(ring, GEN7_SO_WRITE_OFFSET(i));

		intel_ring_emit(ring, 0);

	}



	intel_ring_advance(engine);

	intel_ring_advance(ring);



	return 0;

}
@@ -1256,9 +1254,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 
			       struct drm_i915_gem_execbuffer2 *args,

			       struct list_head *vmas)

{

	struct drm_device *dev = params->dev;

	struct intel_engine_cs *engine = params->engine;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct drm_i915_private *dev_priv = params->request->i915;

	u64 exec_start, exec_len;

	int instp_mode;

	u32 instp_mask;
@@ -1272,34 +1268,31 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 
	if (ret)

		return ret;



	WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<engine->id),

	     "%s didn't clear reload\n", engine->name);



	instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;

	instp_mask = I915_EXEC_CONSTANTS_MASK;

	switch (instp_mode) {

	case I915_EXEC_CONSTANTS_REL_GENERAL:

	case I915_EXEC_CONSTANTS_ABSOLUTE:

	case I915_EXEC_CONSTANTS_REL_SURFACE:

		if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {

		if (instp_mode != 0 && params->engine->id != RCS) {

			DRM_DEBUG("non-0 rel constants mode on non-RCS\n");

			return -EINVAL;

		}



		if (instp_mode != dev_priv->relative_constants_mode) {

			if (INTEL_INFO(dev)->gen < 4) {

			if (INTEL_INFO(dev_priv)->gen < 4) {

				DRM_DEBUG("no rel constants on pre-gen4\n");

				return -EINVAL;

			}



			if (INTEL_INFO(dev)->gen > 5 &&

			if (INTEL_INFO(dev_priv)->gen > 5 &&

			    instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {

				DRM_DEBUG("rel surface constants mode invalid on gen5+\n");

				return -EINVAL;

			}



			/* The HW changed the meaning on this bit on gen6 */

			if (INTEL_INFO(dev)->gen >= 6)

			if (INTEL_INFO(dev_priv)->gen >= 6)

				instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;

		}

		break;
@@ -1308,23 +1301,25 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 
		return -EINVAL;

	}



	if (engine == &dev_priv->engine[RCS] &&

	if (params->engine->id == RCS &&

	    instp_mode != dev_priv->relative_constants_mode) {

		struct intel_ringbuffer *ring = params->request->ringbuf;



		ret = intel_ring_begin(params->request, 4);

		if (ret)

			return ret;



		intel_ring_emit(engine, MI_NOOP);

		intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(engine, INSTPM);

		intel_ring_emit(engine, instp_mask << 16 | instp_mode);

		intel_ring_advance(engine);

		intel_ring_emit(ring, MI_NOOP);

		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(ring, INSTPM);

		intel_ring_emit(ring, instp_mask << 16 | instp_mode);

		intel_ring_advance(ring);



		dev_priv->relative_constants_mode = instp_mode;

	}



	if (args->flags & I915_EXEC_GEN7_SOL_RESET) {

		ret = i915_reset_gen7_sol_offsets(dev, params->request);

		ret = i915_reset_gen7_sol_offsets(params->request);

		if (ret)

			return ret;

	}
@@ -1336,7 +1331,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 
	if (exec_len == 0)

		exec_len = params->batch_obj->base.size;



	ret = engine->dispatch_execbuffer(params->request,

	ret = params->engine->dispatch_execbuffer(params->request,

						  exec_start, exec_len,

						  params->dispatch_flags);

	if (ret)

drivers/gpu/drm/i915/i915_gem_gtt.c

+26 −22
Original line number Diff line number Diff line
@@ -669,6 +669,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req, 
			  unsigned entry,

			  dma_addr_t addr)

{

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_engine_cs *engine = req->engine;

	int ret;
@@ -678,13 +679,13 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req, 
	if (ret)

		return ret;



	intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

	intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));

	intel_ring_emit(engine, upper_32_bits(addr));

	intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

	intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));

	intel_ring_emit(engine, lower_32_bits(addr));

	intel_ring_advance(engine);

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

	intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry));

	intel_ring_emit(ring, upper_32_bits(addr));

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

	intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry));

	intel_ring_emit(ring, lower_32_bits(addr));

	intel_ring_advance(ring);



	return 0;

}
@@ -1660,6 +1661,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) 
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,

			 struct drm_i915_gem_request *req)

{

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_engine_cs *engine = req->engine;

	int ret;
@@ -1672,13 +1674,13 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	if (ret)

		return ret;



	intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));

	intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));

	intel_ring_emit(engine, PP_DIR_DCLV_2G);

	intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));

	intel_ring_emit(engine, get_pd_offset(ppgtt));

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_advance(engine);

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));

	intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));

	intel_ring_emit(ring, PP_DIR_DCLV_2G);

	intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));

	intel_ring_emit(ring, get_pd_offset(ppgtt));

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);



	return 0;

}
@@ -1686,6 +1688,7 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,

			  struct drm_i915_gem_request *req)

{

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_engine_cs *engine = req->engine;

	int ret;
@@ -1698,17 +1701,18 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 
	if (ret)

		return ret;



	intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));

	intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));

	intel_ring_emit(engine, PP_DIR_DCLV_2G);

	intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));

	intel_ring_emit(engine, get_pd_offset(ppgtt));

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_advance(engine);

	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));

	intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine));

	intel_ring_emit(ring, PP_DIR_DCLV_2G);

	intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine));

	intel_ring_emit(ring, get_pd_offset(ppgtt));

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_advance(ring);



	/* XXX: RCS is the only one to auto invalidate the TLBs? */

	if (engine->id != RCS) {

		ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

		ret = engine->flush(req,

				    I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);

		if (ret)

			return ret;

	}

drivers/gpu/drm/i915/intel_display.c

+40 −40
Original line number Diff line number Diff line
@@ -11115,7 +11115,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev, 
				 struct drm_i915_gem_request *req,

				 uint32_t flags)

{

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	u32 flip_mask;

	int ret;
@@ -11131,13 +11131,13 @@ static int intel_gen2_queue_flip(struct drm_device *dev, 
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

	else

		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

	intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_emit(engine, MI_DISPLAY_FLIP |

	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_emit(ring, MI_DISPLAY_FLIP |

			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

	intel_ring_emit(engine, fb->pitches[0]);

	intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(engine, 0); /* aux display base address, unused */

	intel_ring_emit(ring, fb->pitches[0]);

	intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(ring, 0); /* aux display base address, unused */



	return 0;

}
@@ -11149,7 +11149,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev, 
				 struct drm_i915_gem_request *req,

				 uint32_t flags)

{

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	u32 flip_mask;

	int ret;
@@ -11162,13 +11162,13 @@ static int intel_gen3_queue_flip(struct drm_device *dev, 
		flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;

	else

		flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;

	intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |

	intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);

	intel_ring_emit(ring, MI_NOOP);

	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |

			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

	intel_ring_emit(engine, fb->pitches[0]);

	intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(engine, MI_NOOP);

	intel_ring_emit(ring, fb->pitches[0]);

	intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(ring, MI_NOOP);



	return 0;

}
@@ -11180,7 +11180,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev, 
				 struct drm_i915_gem_request *req,

				 uint32_t flags)

{

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint32_t pf, pipesrc;
@@ -11194,10 +11194,10 @@ static int intel_gen4_queue_flip(struct drm_device *dev, 
	 * Display Registers (which do not change across a page-flip)

	 * so we need only reprogram the base address.

	 */

	intel_ring_emit(engine, MI_DISPLAY_FLIP |

	intel_ring_emit(ring, MI_DISPLAY_FLIP |

			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

	intel_ring_emit(engine, fb->pitches[0]);

	intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset |

	intel_ring_emit(ring, fb->pitches[0]);

	intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |

			obj->tiling_mode);



	/* XXX Enabling the panel-fitter across page-flip is so far
@@ -11206,7 +11206,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev, 
	 */

	pf = 0;

	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

	intel_ring_emit(engine, pf | pipesrc);

	intel_ring_emit(ring, pf | pipesrc);



	return 0;

}
@@ -11218,7 +11218,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev, 
				 struct drm_i915_gem_request *req,

				 uint32_t flags)

{

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint32_t pf, pipesrc;
@@ -11228,10 +11228,10 @@ static int intel_gen6_queue_flip(struct drm_device *dev, 
	if (ret)

		return ret;



	intel_ring_emit(engine, MI_DISPLAY_FLIP |

	intel_ring_emit(ring, MI_DISPLAY_FLIP |

			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));

	intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);

	intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);

	intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);



	/* Contrary to the suggestions in the documentation,

	 * "Enable Panel Fitter" does not seem to be required when page
@@ -11241,7 +11241,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev, 
	 */

	pf = 0;

	pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;

	intel_ring_emit(engine, pf | pipesrc);

	intel_ring_emit(ring, pf | pipesrc);



	return 0;

}
@@ -11253,7 +11253,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, 
				 struct drm_i915_gem_request *req,

				 uint32_t flags)

{

	struct intel_engine_cs *engine = req->engine;

	struct intel_ringbuffer *ring = req->ringbuf;

	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

	uint32_t plane_bit = 0;

	int len, ret;
@@ -11274,7 +11274,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev, 
	}



	len = 4;

	if (engine->id == RCS) {

	if (req->engine->id == RCS) {

		len += 6;

		/*

		 * On Gen 8, SRM is now taking an extra dword to accommodate
@@ -11312,30 +11312,30 @@ static int intel_gen7_queue_flip(struct drm_device *dev, 
	 * for the RCS also doesn't appear to drop events. Setting the DERRMR

	 * to zero does lead to lockups within MI_DISPLAY_FLIP.

	 */

	if (engine->id == RCS) {

		intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(engine, DERRMR);

		intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |

	if (req->engine->id == RCS) {

		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));

		intel_ring_emit_reg(ring, DERRMR);

		intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |

					  DERRMR_PIPEB_PRI_FLIP_DONE |

					  DERRMR_PIPEC_PRI_FLIP_DONE));

		if (IS_GEN8(dev))

			intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |

			intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |

					      MI_SRM_LRM_GLOBAL_GTT);

		else

			intel_ring_emit(engine, MI_STORE_REGISTER_MEM |

			intel_ring_emit(ring, MI_STORE_REGISTER_MEM |

					      MI_SRM_LRM_GLOBAL_GTT);

		intel_ring_emit_reg(engine, DERRMR);

		intel_ring_emit(engine, engine->scratch.gtt_offset + 256);

		intel_ring_emit_reg(ring, DERRMR);

		intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);

		if (IS_GEN8(dev)) {

			intel_ring_emit(engine, 0);

			intel_ring_emit(engine, MI_NOOP);

			intel_ring_emit(ring, 0);

			intel_ring_emit(ring, MI_NOOP);

		}

	}



	intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);

	intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));

	intel_ring_emit(engine, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(engine, (MI_NOOP));

	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);

	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));

	intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);

	intel_ring_emit(ring, (MI_NOOP));



	return 0;

}

drivers/gpu/drm/i915/intel_lrc.c

+89 −94

File changed.

Preview size limit exceeded, changes collapsed.