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Commit b503d7ed authored by Kyle Yan's avatar Kyle Yan
Browse files

soc: qcom: pil: Add support for qdspv65.1.0 reset 



Add support for q6v65 modem reset on PIL for qdspv65.1.0. Reset sequence on
software side has been simplified with the introduction of boot FSM.

Change-Id: I6d478b9a62c95c4d28bbf9ab188f4c278014fbe2
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
parent 24c8b94e

Documentation/devicetree/bindings/pil/pil-q6v5-mss.txt

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ Optional properties: 
- qcom,qdsp6v61-1-1: Boolean- Present if the qdsp version is v61 1.1

- qcom,qdsp6v62-1-2: Boolean- Present if the qdsp version is v62 1.2

- qcom,qdsp6v62-1-5: Boolean- Present if the qdsp version is v62 1.5

- qcom,qdsp6v65-1-0: Boolean- Present if the qdsp version is v65 1.0

- qcom,mx-spike-wa: Boolean- Present if we need to assert QDSP6 I/O clamp, memory

		    wordline clamp, and compiler memory clamp during MSS restart.

- qcom,qdsp6v56-1-10: Boolean- Present if the qdsp version is v56 1.10

drivers/soc/qcom/pil-q6v5.c

+55 −1
Original line number Diff line number Diff line
@@ -79,6 +79,14 @@ 
#define BHS_CHECK_MAX_LOOPS             (200)

#define QDSP6SS_XO_CBCR                 (0x0038)



/* QDSP6v65 parameters */

#define QDSP6SS_BOOT_CORE_START		(0x400)

#define QDSP6SS_BOOT_CMD		(0x404)

#define QDSP6SS_BOOT_STATUS		(0x408)

#define QDSP6SS_SLEEP			(0x3C)

#define SLEEP_CHECK_MAX_LOOPS		(200)

#define BOOT_FSM_TIMEOUT		(10)



#define QDSP6SS_ACC_OVERRIDE_VAL	0x20



int pil_q6v5_make_proxy_votes(struct pil_desc *pil)
@@ -353,6 +361,46 @@ static int q6v55_branch_clk_enable(struct q6v5_data *drv) 
	return -EINVAL;

}



static int __pil_q6v65_reset(struct pil_desc *pil)

{

	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);

	u32 val, count;

	unsigned long timeout;



	val = readl_relaxed(drv->reg_base + QDSP6SS_SLEEP);

	val |= 0x1;

	writel_relaxed(val, drv->reg_base + QDSP6SS_SLEEP);

	for (count = SLEEP_CHECK_MAX_LOOPS; count > 0; count--) {

		val = readl_relaxed(drv->reg_base + QDSP6SS_SLEEP);

		if (!(val & BIT(31)))

			break;

		udelay(1);

	}



	if (!count) {

		dev_err(drv->desc.dev, "Sleep clock did not come on in time\n");

		return -ETIMEDOUT;

	}



	/* De-assert QDSP6 stop core */

	writel_relaxed(1, drv->reg_base + QDSP6SS_BOOT_CORE_START);

	/* De-assert stop core before starting boot FSM */

	mb();

	/* Trigger boot FSM */

	writel_relaxed(1, drv->reg_base + QDSP6SS_BOOT_CMD);



	/* Wait for boot FSM to complete */

	timeout = jiffies + usecs_to_jiffies(BOOT_FSM_TIMEOUT);

	while (time_before(jiffies, timeout)) {

		val = readl_relaxed(drv->reg_base + QDSP6SS_BOOT_STATUS);

		if (val & BIT(0))

			return 0;

	}



	dev_err(drv->desc.dev, "Boot FSM failed to complete.\n");

	return -ETIMEDOUT;

}



static int __pil_q6v55_reset(struct pil_desc *pil)

{

	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);
@@ -556,7 +604,10 @@ int pil_q6v5_reset(struct pil_desc *pil) 
{

	struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc);



	if (drv->qdsp6v55)



	if (drv->qdsp6v65_1_0)

		return __pil_q6v65_reset(pil);

	else if (drv->qdsp6v55)

		return __pil_q6v55_reset(pil);

	else

		return __pil_q6v5_reset(pil);
@@ -673,6 +724,9 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) 
	drv->qdsp6v62_1_5 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v62-1-5");



	drv->qdsp6v65_1_0 = of_property_read_bool(pdev->dev.of_node,

						"qcom,qdsp6v65-1-0");



	drv->non_elf_image = of_property_read_bool(pdev->dev.of_node,

						"qcom,mba-image-is-not-elf");

drivers/soc/qcom/pil-q6v5.h

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ struct q6v5_data { 
	bool qdsp6v61_1_1;

	bool qdsp6v62_1_2;

	bool qdsp6v62_1_5;

	bool qdsp6v65_1_0;

	bool non_elf_image;

	bool restart_reg_sec;

	bool override_acc;