Merge tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

* Mediatek IOMMU Architecture Implementation

  Some Mediatek SOCs contain a Multimedia Memory Management Unit (M4U) which

uses the ARM Short-Descriptor translation table format for address translation.

  About the M4U Hardware Block Diagram, please check below:

              EMI (External Memory Interface)

               |

              m4u (Multimedia Memory Management Unit)

               |

           SMI Common(Smart Multimedia Interface Common)

               |

       +----------------+-------

       |                |

       |                |

   SMI larb0        SMI larb1   ... SoCs have several SMI local arbiter(larb).

   (display)         (vdec)

       |                |

       |                |

 +-----+-----+     +----+----+

 |     |     |     |    |    |

 |     |     |...  |    |    |  ... There are different ports in each larb.

 |     |     |     |    |    |

OVL0 RDMA0 WDMA0  MC   PP   VLD

  As above, The Multimedia HW will go through SMI and M4U while it

access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain

smi local arbiter and smi common. It will control whether the Multimedia

HW should go though the m4u for translation or bypass it and talk

directly with EMI. And also SMI help control the power domain and clocks for

each local arbiter.

  Normally we specify a local arbiter(larb) for each multimedia HW

like display, video decode, and camera. And there are different ports

in each larb. Take a example, There are many ports like MC, PP, VLD in the

video decode local arbiter, all these ports are according to the video HW.

Required properties:

- compatible : must be "mediatek,mt8173-m4u".

- reg : m4u register base and size.

- interrupts : the interrupt of m4u.

- clocks : must contain one entry for each clock-names.

- clock-names : must be "bclk", It is the block clock of m4u.

- mediatek,larbs : List of phandle to the local arbiters in the current Socs.

	Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort

	according to the local arbiter index, like larb0, larb1, larb2...

- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.

	Specifies the mtk_m4u_id as defined in

	dt-binding/memory/mt8173-larb-port.h.

Example:

	iommu: iommu@10205000 {

		compatible = "mediatek,mt8173-m4u";

		reg = <0 0x10205000 0 0x1000>;

		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;

		clocks = <&infracfg CLK_INFRA_M4U>;

		clock-names = "bclk";

		mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 &larb4 &larb5>;

		#iommu-cells = <1>;

	};

Example for a client device:

	display {

		compatible = "mediatek,mt8173-disp";

		iommus = <&iommu M4U_PORT_DISP_OVL0>,

			 <&iommu M4U_PORT_DISP_RDMA0>;

		...

	};

Required Properties:

  - compatible: Must contain SoC-specific and generic entries from below.

  - compatible: Must contain SoC-specific and generic entry below in case

    the device is compatible with the R-Car Gen2 VMSA-compatible IPMMU.

    - "renesas,ipmmu-r8a73a4" for the R8A73A4 (R-Mobile APE6) IPMMU.

    - "renesas,ipmmu-r8a7790" for the R8A7790 (R-Car H2) IPMMU.

    - "renesas,ipmmu-r8a7791" for the R8A7791 (R-Car M2-W) IPMMU.

    - "renesas,ipmmu-r8a7793" for the R8A7793 (R-Car M2-N) IPMMU.

    - "renesas,ipmmu-r8a7794" for the R8A7794 (R-Car E2) IPMMU.

    - "renesas,ipmmu-r8a7795" for the R8A7795 (R-Car H3) IPMMU.

    - "renesas,ipmmu-vmsa" for generic R-Car Gen2 VMSA-compatible IPMMU.

  - reg: Base address and size of the IPMMU registers.

  - interrupts: Specifiers for the MMU fault interrupts. For instances that

    support secure mode two interrupts must be specified, for non-secure and

    secure mode, in that order. For instances that don't support secure mode a

    single interrupt must be specified.

    single interrupt must be specified. Not required for cache IPMMUs.

  - #iommu-cells: Must be 1.

Optional properties:

  - renesas,ipmmu-main: reference to the main IPMMU instance in two cells.

    The first cell is a phandle to the main IPMMU and the second cell is

    the interrupt bit number associated with the particular cache IPMMU device.

    The interrupt bit number needs to match the main IPMMU IMSSTR register.

    Only used by cache IPMMU instances.

Each bus master connected to an IPMMU must reference the IPMMU in its device

node with the following property:

  for window 1, 2 and 3.

* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and

  the other System MMU on the write channel.

The drivers must consider how to handle those System MMUs. One of the idea is

to implement child devices or sub-devices which are the client devices of the

System MMU.

Note:

The current DT binding for the Exynos System MMU is incomplete.

The following properties can be removed or changed, if found incompatible with

the "Generic IOMMU Binding" support for attaching devices to the IOMMU.

For information on assigning System MMU controller to its peripheral devices,

see generic IOMMU bindings.

Required properties:

- compatible: Should be "samsung,exynos-sysmmu"

- reg: A tuple of base address and size of System MMU registers.

- #iommu-cells: Should be <0>.

- interrupt-parent: The phandle of the interrupt controller of System MMU

- interrupts: An interrupt specifier for interrupt signal of System MMU,

	      according to the format defined by a particular interrupt

	      controller.

- clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.

- clock-names: Should be "sysmmu" or a pair of "aclk" and "pclk" to gate

	       SYSMMU core clocks.

	       Optional "master" if the clock to the System MMU is gated by

	       another gate clock other than "sysmmu".

	       Exynos4 SoCs, there needs no "master" clock.

	       Exynos5 SoCs, some System MMUs must have "master" clocks.

- clocks: Required if the System MMU is needed to gate its clock.

	       another gate clock other core  (usually main gate clock

	       of peripheral device this SYSMMU belongs to).

- clocks: Phandles for respective clocks described by clock-names.

- power-domains: Required if the System MMU is needed to gate its power.

	  Please refer to the following document:

	  Documentation/devicetree/bindings/power/pd-samsung.txt

		power-domains = <&pd_gsc>;

		clocks = <&clock CLK_GSCL0>;

		clock-names = "gscl";

		iommus = <&sysmmu_gsc0>;

	};

	sysmmu_gsc0: sysmmu@13E80000 {

		clock-names = "sysmmu", "master";

		clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;

		power-domains = <&pd_gsc>;

		#iommu-cells = <0>;

	};

SMI (Smart Multimedia Interface) Common

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Required properties:

- compatible : must be "mediatek,mt8173-smi-common"

- reg : the register and size of the SMI block.

- power-domains : a phandle to the power domain of this local arbiter.

- clocks : Must contain an entry for each entry in clock-names.

- clock-names : must contain 2 entries, as follows:

  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting

	    the register.

  - "smi" : It's the clock for transfer data and command.

  They may be the same if both source clocks are the same.

Example:

	smi_common: smi@14022000 {

		compatible = "mediatek,mt8173-smi-common";

		reg = <0 0x14022000 0 0x1000>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

		clocks = <&mmsys CLK_MM_SMI_COMMON>,

			 <&mmsys CLK_MM_SMI_COMMON>;

		clock-names = "apb", "smi";

	};

SMI (Smart Multimedia Interface) Local Arbiter

The hardware block diagram please check bindings/iommu/mediatek,iommu.txt

Required properties:

- compatible : must be "mediatek,mt8173-smi-larb"

- reg : the register and size of this local arbiter.

- mediatek,smi : a phandle to the smi_common node.

- power-domains : a phandle to the power domain of this local arbiter.

- clocks : Must contain an entry for each entry in clock-names.

- clock-names: must contain 2 entries, as follows:

  - "apb" : Advanced Peripheral Bus clock, It's the clock for setting

	    the register.

  - "smi" : It's the clock for transfer data and command.

Example:

	larb1: larb@16010000 {

		compatible = "mediatek,mt8173-smi-larb";

		reg = <0 0x16010000 0 0x1000>;

		mediatek,smi = <&smi_common>;

		power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;

		clocks = <&vdecsys CLK_VDEC_CKEN>,

			 <&vdecsys CLK_VDEC_LARB_CKEN>;

		clock-names = "apb", "smi";

	};