Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b465646e authored by Hans de Goede's avatar Hans de Goede Committed by Ulf Hansson
Browse files

mmc: sunxi: sun4i / sun5i do not have sample clocks 



It turns out that sun4i (A10) and sun5i (A13 & co) do not have sample
clocks, so add a new sun7i-a20-mmc compatible and do not try to use
sample clocks on sun4i / sun5i.

Since sun4i / sun5i do not have sample clocks, they cannot (reliably) do
DDR rates, so only set MMC_CAP_1_8V_DDR when we do have sample clks.

Note this patch leaves the clk_prepare_enable() / clk_disable_unprepare()
calls to the sample clks as-is, without adding checks for them being
NULL. All the clk_foo calls accept a NULL clk and will return success when
called with a NULL clk.

Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent f2cecb70

Documentation/devicetree/bindings/mmc/sunxi-mmc.txt

+5 −1
Original line number Diff line number Diff line
@@ -8,7 +8,11 @@ as the speed of SD standard 3.0. 
Absolute maximum transfer rate is 200MB/s



Required properties:

 - compatible : "allwinner,sun4i-a10-mmc" or "allwinner,sun5i-a13-mmc"

 - compatible : should be one of:

   * "allwinner,sun4i-a10-mmc"

   * "allwinner,sun5i-a13-mmc"

   * "allwinner,sun7i-a20-mmc"

   * "allwinner,sun9i-a80-mmc"

 - reg : mmc controller base registers

 - clocks : a list with 4 phandle + clock specifier pairs

 - clock-names : must contain "ahb", "mmc", "output" and "sample"

drivers/mmc/host/sunxi-mmc.c

+24 −11
Original line number Diff line number Diff line
@@ -662,6 +662,9 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 
{

	int index;



	if (!host->cfg->clk_delays)

		return 0;



	/* determine delays */

	if (rate <= 400000) {

		index = SDXC_CLK_400K;
@@ -978,10 +981,15 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 


static const struct sunxi_mmc_cfg sun4i_a10_cfg = {

	.idma_des_size_bits = 13,

	.clk_delays = sunxi_mmc_clk_delays,

	.clk_delays = NULL,

};



static const struct sunxi_mmc_cfg sun5i_a13_cfg = {

	.idma_des_size_bits = 16,

	.clk_delays = NULL,

};



static const struct sunxi_mmc_cfg sun7i_a20_cfg = {

	.idma_des_size_bits = 16,

	.clk_delays = sunxi_mmc_clk_delays,

};
@@ -994,6 +1002,7 @@ static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 
static const struct of_device_id sunxi_mmc_of_match[] = {

	{ .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg },

	{ .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg },

	{ .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg },

	{ .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg },

	{ /* sentinel */ }

};
@@ -1032,6 +1041,7 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 
		return PTR_ERR(host->clk_mmc);

	}



	if (host->cfg->clk_delays) {

		host->clk_output = devm_clk_get(&pdev->dev, "output");

		if (IS_ERR(host->clk_output)) {

			dev_err(&pdev->dev, "Could not get output clock\n");
@@ -1043,6 +1053,7 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 
			dev_err(&pdev->dev, "Could not get sample clock\n");

			return PTR_ERR(host->clk_sample);

		}

	}



	host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");

	if (PTR_ERR(host->reset) == -EPROBE_DEFER)
@@ -1144,9 +1155,11 @@ static int sunxi_mmc_probe(struct platform_device *pdev) 
	mmc->f_min		=   400000;

	mmc->f_max		= 52000000;

	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |

				  MMC_CAP_1_8V_DDR |

				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;



	if (host->cfg->clk_delays)

		mmc->caps      |= MMC_CAP_1_8V_DDR;



	ret = mmc_of_parse(mmc);

	if (ret)

		goto error_free_dma;