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Commit b42a9f44 authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
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Blackfin arch: fix missing digit in SCLK range checking

parent 7e1e7aed
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+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@
#define SDRAM_tRCD      TRCD_2
#define SDRAM_tWR       TWR_2
#endif
#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
#define SDRAM_tRP       TRP_2
#define SDRAM_tRP_num   2
#define SDRAM_tRAS      TRAS_5