Loading drivers/gpu/msm/adreno_a6xx.c +22 −24 Original line number Diff line number Diff line Loading @@ -116,34 +116,29 @@ static void a6xx_init(struct adreno_device *adreno_dev) static void a6xx_protect_init(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_protected_registers *mmu_prot = NULL; int i; int num_sets; int num_sets_array; unsigned int mmu_base; unsigned int mmu_range; struct kgsl_protected_registers *mmu_prot = kgsl_mmu_get_prot_regs(&device->mmu); int i, num_sets; int req_sets = ARRAY_SIZE(a6xx_protected_regs_group); int max_sets = adreno_dev->gpucore->num_protected_regs; unsigned int mmu_base = 0, mmu_range = 0, cur_range; /* enable access protection to privileged registers */ kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000007); num_sets = ARRAY_SIZE(a6xx_protected_regs_group); mmu_prot = kgsl_mmu_get_prot_regs(&device->mmu); if (mmu_prot) { mmu_base = mmu_prot->base; mmu_range = 1 << mmu_prot->range; num_sets += DIV_ROUND_UP(mmu_range, 0x2000); req_sets += DIV_ROUND_UP(mmu_range, 0x2000); } if (num_sets > adreno_dev->gpucore->num_protected_regs) { if (req_sets > max_sets) WARN(1, "Size exceeds the num of protection regs available\n"); num_sets = adreno_dev->gpucore->num_protected_regs; } num_sets_array = min_t(unsigned int, ARRAY_SIZE(a6xx_protected_regs_group), num_sets); for (i = 0; i < num_sets_array; i++) { /* Protect GPU registers */ num_sets = min_t(unsigned int, ARRAY_SIZE(a6xx_protected_regs_group), max_sets); for (i = 0; i < num_sets; i++) { struct a6xx_protected_regs *regs = &a6xx_protected_regs_group[i]; Loading @@ -152,15 +147,18 @@ static void a6xx_protect_init(struct adreno_device *adreno_dev) (regs->read_protect << 31)); } for (; i < num_sets; i++) { unsigned int cur_range = min_t(unsigned int, mmu_range, /* Protect MMU registers */ if (mmu_prot) { while ((i < max_sets) && (mmu_range > 0)) { cur_range = min_t(unsigned int, mmu_range, 0x2000); kgsl_regwrite(device, A6XX_CP_PROTECT_REG + i, mmu_base | ((cur_range - 1) << 18) | (1 << 31)); mmu_base += cur_range; mmu_range -= cur_range; i++; } } } Loading Loading
drivers/gpu/msm/adreno_a6xx.c +22 −24 Original line number Diff line number Diff line Loading @@ -116,34 +116,29 @@ static void a6xx_init(struct adreno_device *adreno_dev) static void a6xx_protect_init(struct adreno_device *adreno_dev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct kgsl_protected_registers *mmu_prot = NULL; int i; int num_sets; int num_sets_array; unsigned int mmu_base; unsigned int mmu_range; struct kgsl_protected_registers *mmu_prot = kgsl_mmu_get_prot_regs(&device->mmu); int i, num_sets; int req_sets = ARRAY_SIZE(a6xx_protected_regs_group); int max_sets = adreno_dev->gpucore->num_protected_regs; unsigned int mmu_base = 0, mmu_range = 0, cur_range; /* enable access protection to privileged registers */ kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000007); num_sets = ARRAY_SIZE(a6xx_protected_regs_group); mmu_prot = kgsl_mmu_get_prot_regs(&device->mmu); if (mmu_prot) { mmu_base = mmu_prot->base; mmu_range = 1 << mmu_prot->range; num_sets += DIV_ROUND_UP(mmu_range, 0x2000); req_sets += DIV_ROUND_UP(mmu_range, 0x2000); } if (num_sets > adreno_dev->gpucore->num_protected_regs) { if (req_sets > max_sets) WARN(1, "Size exceeds the num of protection regs available\n"); num_sets = adreno_dev->gpucore->num_protected_regs; } num_sets_array = min_t(unsigned int, ARRAY_SIZE(a6xx_protected_regs_group), num_sets); for (i = 0; i < num_sets_array; i++) { /* Protect GPU registers */ num_sets = min_t(unsigned int, ARRAY_SIZE(a6xx_protected_regs_group), max_sets); for (i = 0; i < num_sets; i++) { struct a6xx_protected_regs *regs = &a6xx_protected_regs_group[i]; Loading @@ -152,15 +147,18 @@ static void a6xx_protect_init(struct adreno_device *adreno_dev) (regs->read_protect << 31)); } for (; i < num_sets; i++) { unsigned int cur_range = min_t(unsigned int, mmu_range, /* Protect MMU registers */ if (mmu_prot) { while ((i < max_sets) && (mmu_range > 0)) { cur_range = min_t(unsigned int, mmu_range, 0x2000); kgsl_regwrite(device, A6XX_CP_PROTECT_REG + i, mmu_base | ((cur_range - 1) << 18) | (1 << 31)); mmu_base += cur_range; mmu_range -= cur_range; i++; } } } Loading