Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b3bf41be authored by Ben Dooks's avatar Ben Dooks
Browse files

ARM: SAMSUNG: Reduce size of struct clk. 



Reduce the size of struct clk by 12 bytes and make defining clocks with
common implementation functions easier by moving the set_rate, get_rate,
round_rate and set_parent calls into a new structure called 'struct clk_ops'
and using that instead.

This change does make a few clocks larger as they need their own clk_ops,
but this is outweighed by the number of clocks with either no ops or having
a common set of ops.

Update all the users of this.

Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
parent 13bbd885

arch/arm/mach-s3c2412/clock.c

+33 −19
Original line number Diff line number Diff line
@@ -124,7 +124,9 @@ static struct clk clk_usysclk = { 
	.name		= "usysclk",

	.id		= -1,

	.parent		= &clk_xtal,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_usysclk,

	},

};



static struct clk clk_mrefclk = {
@@ -199,10 +201,12 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate) 
static struct clk clk_usbsrc = {

	.name		= "usbsrc",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_usbsrc,

		.set_rate	= s3c2412_setrate_usbsrc,

		.round_rate	= s3c2412_roundrate_usbsrc,

		.set_parent	= s3c2412_setparent_usbsrc,

	},

};



static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -225,7 +229,9 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent) 
static struct clk clk_msysclk = {

	.name		= "msysclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_msysclk,

	},

};



static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
@@ -264,7 +270,9 @@ static struct clk clk_armclk = { 
	.name		= "armclk",

	.id		= -1,

	.parent		= &clk_msysclk,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2412_setparent_armclk,

	},

};



/* these next clocks have an divider immediately after them,
@@ -337,10 +345,12 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate) 
static struct clk clk_uart = {

	.name		= "uartclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_uart,

		.set_rate	= s3c2412_setrate_uart,

		.set_parent	= s3c2412_setparent_uart,

		.round_rate	= s3c2412_roundrate_clksrc,

	},

};



static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
@@ -388,10 +398,12 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate) 
static struct clk clk_i2s = {

	.name		= "i2sclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_i2s,

		.set_rate	= s3c2412_setrate_i2s,

		.set_parent	= s3c2412_setparent_i2s,

		.round_rate	= s3c2412_roundrate_clksrc,

	},

};



static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
@@ -438,10 +450,12 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate) 
static struct clk clk_cam = {

	.name		= "camif-upll",	/* same as 2440 name */

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2412_getrate_cam,

		.set_rate	= s3c2412_setrate_cam,

		.set_parent	= s3c2412_setparent_cam,

		.round_rate	= s3c2412_roundrate_clksrc,

	},

};



/* standard clock definitions */

arch/arm/mach-s3c2440/clock.c

+4 −2
Original line number Diff line number Diff line
@@ -98,8 +98,10 @@ static struct clk s3c2440_clk_cam = { 
static struct clk s3c2440_clk_cam_upll = {

	.name		= "camif-upll",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_rate	= s3c2440_camif_upll_setrate,

		.round_rate	= s3c2440_camif_upll_round,

	},

};



static struct clk s3c2440_clk_ac97 = {

arch/arm/mach-s3c2442/clock.c

+4 −2
Original line number Diff line number Diff line
@@ -109,8 +109,10 @@ static struct clk s3c2442_clk_cam = { 
static struct clk s3c2442_clk_cam_upll = {

	.name		= "camif-upll",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_rate	= s3c2442_camif_upll_setrate,

		.round_rate	= s3c2442_camif_upll_round,

	},

};



static int s3c2442_clk_add(struct sys_device *sysdev)

arch/arm/mach-s3c2443/clock.c

+59 −29
Original line number Diff line number Diff line
@@ -187,7 +187,9 @@ static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent) 
static struct clk clk_epllref = {

	.name		= "epllref",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_epllref,

	},

};



static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
@@ -205,7 +207,9 @@ static struct clk clk_mdivclk = { 
	.name		= "mdivclk",

	.parent		= &clk_mpllref,

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_mdivclk,

	},

};



static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
@@ -232,7 +236,9 @@ static struct clk clk_msysclk = { 
	.name		= "msysclk",

	.parent		= &clk_xtal,

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_msysclk,

	},

};



/* armdiv
@@ -273,7 +279,9 @@ static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent) 
static struct clk clk_arm = {

	.name		= "armclk",

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_armclk,

	},

};



/* esysclk
@@ -302,7 +310,9 @@ static struct clk clk_esysclk = { 
	.name		= "esysclk",

	.parent		= &clk_epll,

	.id		= -1,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_esysclk,

	},

};



/* uartclk
@@ -341,9 +351,11 @@ static struct clk clk_uart = { 
	.name		= "uartclk",

	.id		= -1,

	.parent		= &clk_esysclk,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_uart,

		.set_rate	= s3c2443_setrate_uart,

		.round_rate	= s3c2443_roundrate_clksrc16,

	},

};



/* hsspi
@@ -384,9 +396,11 @@ static struct clk clk_hsspi = { 
	.parent		= &clk_esysclk,

	.ctrlbit	= S3C2443_SCLKCON_HSSPICLK,

	.enable		= s3c2443_clkcon_enable_s,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_hsspi,

		.set_rate	= s3c2443_setrate_hsspi,

		.round_rate	= s3c2443_roundrate_clksrc4,

	},

};



/* usbhost
@@ -426,9 +440,11 @@ static struct clk clk_usb_bus_host = { 
	.parent		= &clk_esysclk,

	.ctrlbit	= S3C2443_SCLKCON_USBHOST,

	.enable		= s3c2443_clkcon_enable_s,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_usbhost,

		.set_rate	= s3c2443_setrate_usbhost,

		.round_rate	= s3c2443_roundrate_clksrc4,

	},

};



/* clk_hsmcc_div
@@ -468,9 +484,11 @@ static struct clk clk_hsmmc_div = { 
	.name		= "hsmmc-div",

	.id		= -1,

	.parent		= &clk_esysclk,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_hsmmc_div,

		.set_rate	= s3c2443_setrate_hsmmc_div,

		.round_rate	= s3c2443_roundrate_clksrc4,

	},

};



static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
@@ -505,7 +523,9 @@ static struct clk clk_hsmmc = { 
	.id		= -1,

	.parent		= &clk_hsmmc_div,

	.enable		= s3c2443_enable_hsmmc,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_hsmmc,

	},

};



/* i2s_eplldiv
@@ -543,9 +563,11 @@ static struct clk clk_i2s_eplldiv = { 
	.name		= "i2s-eplldiv",

	.id		= -1,

	.parent		= &clk_esysclk,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_i2s_eplldiv,

		.set_rate	= s3c2443_setrate_i2s_eplldiv,

		.round_rate	= s3c2443_roundrate_clksrc16,

	},

};



/* i2s-ref
@@ -578,7 +600,9 @@ static struct clk clk_i2s = { 
	.parent		= &clk_i2s_eplldiv,

	.ctrlbit	= S3C2443_SCLKCON_I2SCLK,

	.enable		= s3c2443_clkcon_enable_s,

	.ops		= &(struct clk_ops) {

		.set_parent	= s3c2443_setparent_i2s,

	},

};



/* cam-if
@@ -618,9 +642,11 @@ static struct clk clk_cam = { 
	.parent		= &clk_esysclk,

	.ctrlbit	= S3C2443_SCLKCON_CAMCLK,

	.enable		= s3c2443_clkcon_enable_s,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_cam,

		.set_rate	= s3c2443_setrate_cam,

		.round_rate	= s3c2443_roundrate_clksrc16,

	},

};



/* display-if
@@ -660,9 +686,11 @@ static struct clk clk_display = { 
	.parent		= &clk_esysclk,

	.ctrlbit	= S3C2443_SCLKCON_DISPCLK,

	.enable		= s3c2443_clkcon_enable_s,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_getrate_display,

		.set_rate	= s3c2443_setrate_display,

		.round_rate	= s3c2443_roundrate_clksrc256,

	},

};



/* prediv
@@ -685,7 +713,9 @@ static struct clk clk_prediv = { 
	.name		= "prediv",

	.id		= -1,

	.parent		= &clk_msysclk,

	.ops		= &(struct clk_ops) {

		.get_rate	= s3c2443_prediv_getrate,

	},

};



/* standard clock definitions */

arch/arm/plat-s3c/clock.c

+17 −14
Original line number Diff line number Diff line
@@ -150,8 +150,8 @@ unsigned long clk_get_rate(struct clk *clk) 
	if (clk->rate != 0)

		return clk->rate;



	if (clk->get_rate != NULL)

		return (clk->get_rate)(clk);

	if (clk->ops != NULL && clk->ops->get_rate != NULL)

		return (clk->ops->get_rate)(clk);



	if (clk->parent != NULL)

		return clk_get_rate(clk->parent);
@@ -161,8 +161,8 @@ unsigned long clk_get_rate(struct clk *clk) 


long clk_round_rate(struct clk *clk, unsigned long rate)

{

	if (!IS_ERR(clk) && clk->round_rate)

		return (clk->round_rate)(clk, rate);

	if (!IS_ERR(clk) && clk->ops && clk->ops->round_rate)

		return (clk->ops->round_rate)(clk, rate);



	return rate;

}
@@ -178,13 +178,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate) 
	 * the clock may have been made this way by choice.

	 */



	WARN_ON(clk->set_rate == NULL);

	WARN_ON(clk->ops == NULL);

	WARN_ON(clk->ops && clk->ops->set_rate == NULL);



	if (clk->set_rate == NULL)

	if (clk->ops == NULL || clk->ops->set_rate == NULL)

		return -EINVAL;



	spin_lock(&clocks_lock);

	ret = (clk->set_rate)(clk, rate);

	ret = (clk->ops->set_rate)(clk, rate);

	spin_unlock(&clocks_lock);



	return ret;
@@ -204,8 +205,8 @@ int clk_set_parent(struct clk *clk, struct clk *parent) 


	spin_lock(&clocks_lock);



	if (clk->set_parent)

		ret = (clk->set_parent)(clk, parent);

	if (clk->ops && clk->ops->set_parent)

		ret = (clk->ops->set_parent)(clk, parent);



	spin_unlock(&clocks_lock);
@@ -230,6 +231,10 @@ static int clk_default_setrate(struct clk *clk, unsigned long rate) 
	return 0;

}



static struct clk_ops clk_ops_def_setrate = {

	.set_rate	= clk_default_setrate,

};



struct clk clk_xtal = {

	.name		= "xtal",

	.id		= -1,
@@ -251,7 +256,7 @@ struct clk clk_epll = { 
struct clk clk_mpll = {

	.name		= "mpll",

	.id		= -1,

	.set_rate	= clk_default_setrate,

	.ops		= &clk_ops_def_setrate,

};



struct clk clk_upll = {
@@ -267,7 +272,6 @@ struct clk clk_f = { 
	.rate		= 0,

	.parent		= &clk_mpll,

	.ctrlbit	= 0,

	.set_rate	= clk_default_setrate,

};



struct clk clk_h = {
@@ -276,7 +280,7 @@ struct clk clk_h = { 
	.rate		= 0,

	.parent		= NULL,

	.ctrlbit	= 0,

	.set_rate	= clk_default_setrate,

	.ops		= &clk_ops_def_setrate,

};



struct clk clk_p = {
@@ -285,7 +289,7 @@ struct clk clk_p = { 
	.rate		= 0,

	.parent		= NULL,

	.ctrlbit	= 0,

	.set_rate	= clk_default_setrate,

	.ops		= &clk_ops_def_setrate,

};



struct clk clk_usb_bus = {
@@ -296,7 +300,6 @@ struct clk clk_usb_bus = { 
};







struct clk s3c24xx_uclk = {

	.name		= "uclk",

	.id		= -1,