Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit b324252c authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
Browse files

ARM: shmobile: r8a7791: add CAN clocks 



The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock (clkp2)
and external clock fed on CAN_CLK pin.  Describe those clocks in the device
tree,  along with  the USB_EXTAL clock  from which clkp2 is derived.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 6a7742b4

arch/arm/boot/dts/r8a7791.dtsi

+21 −2
Original line number Diff line number Diff line
@@ -862,15 +862,34 @@ 
			status = "disabled";

		};



		/* External USB clock - can be overridden by the board */

		usb_extal_clk: usb_extal_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <48000000>;

			clock-output-names = "usb_extal";

		};



		/* External CAN clock */

		can_clk: can_clk {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			/* This value must be overridden by the board. */

			clock-frequency = <0>;

			clock-output-names = "can_clk";

			status = "disabled";

		};



		/* Special CPG clocks */

		cpg_clocks: cpg_clocks@e6150000 {

			compatible = "renesas,r8a7791-cpg-clocks",

				     "renesas,rcar-gen2-cpg-clocks";

			reg = <0 0xe6150000 0 0x1000>;

			clocks = <&extal_clk>;

			clocks = <&extal_clk &usb_extal_clk>;

			#clock-cells = <1>;

			clock-output-names = "main", "pll0", "pll1", "pll3",

					     "lb", "qspi", "sdh", "sd0", "z";

					     "lb", "qspi", "sdh", "sd0", "z",

					     "rcan";

		};



		/* Variable factor clocks */

include/dt-bindings/clock/r8a7791-clock.h

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define R8A7791_CLK_SDH			6

#define R8A7791_CLK_SD0			7

#define R8A7791_CLK_Z			8

#define R8A7791_CLK_RCAN		9



/* MSTP0 */

#define R8A7791_CLK_MSIOF0		0